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SN8P2614 Series
8-Bit Micro-Controller
SN8P2614
USER'S MANUAL
Preliminary V 0.3
SN8P2614
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
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Preliminary Version 0.3
SN8P2614 Series
8-Bit Micro-Controller
AMENDMENT HISTORY
Version VER 0.1 VER 0.2 VER 0.3 Date Jun. 2006 Jun. 2006 Feb. 2007 Description First issue Add P1, P2 application circuit. 1. Add Marking Definition. 2. Modify ELECTRICAL CHARACTERISTIC. 3. Modify RST/P0.2/VPP PIN DISCRIPTION.
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8-Bit Micro-Controller
Table of Content
AMENDMENT HISTORY ............................................................................................................................ 2 1 1 PRODUCT OVERVIEW......................................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 2 2 FEATURES ........................................................................................................................................ 7 SYSTEM BLOCK DIAGRAM .......................................................................................................... 8 PIN ASSIGNMENT ........................................................................................................................... 9 PIN DESCRIPTIONS....................................................................................................................... 10 PIN CIRCUIT DIAGRAMS............................................................................................................. 11
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 12 2.1 MEMORY MAP............................................................................................................................... 12
2.1.1 PROGRAM MEMORY (ROM) ................................................................................................. 12 2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 13 2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 14 2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 16 2.1.1.4 JUMP TABLE DESCRIPTION ........................................................................................... 18 2.1.1.5 CHECKSUM CALCULATION........................................................................................... 20 2.1.2 CODE OPTION TABLE ........................................................................................................... 21 2.1.3 DATA MEMORY (RAM)........................................................................................................... 22 2.1.4 SYSTEM REGISTER................................................................................................................. 23 2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 23 2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 23 2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 24 2.1.4.4 ACCUMULATOR ............................................................................................................... 25 2.1.4.5 PROGRAM FLAG ............................................................................................................... 26 2.1.4.6 PROGRAM COUNTER....................................................................................................... 27 2.1.4.7 H, L REGISTERS................................................................................................................. 30 2.1.4.8 Y, Z REGISTERS................................................................................................................. 31 2.1.4.9 R REGISTERS ..................................................................................................................... 32 2.2 ADDRESSING MODE .................................................................................................................... 33 2.2.1 IMMEDIATE ADDRESSING MODE....................................................................................... 33 2.2.2 DIRECTLY ADDRESSING MODE .......................................................................................... 33 2.2.3 INDIRECTLY ADDRESSING MODE ...................................................................................... 33 2.3 STACK OPERATION...................................................................................................................... 34 2.3.1 2.3.2 2.3.3 OVERVIEW .............................................................................................................................. 34 STACK REGISTERS ................................................................................................................. 35 STACK OPERATION EXAMPLE............................................................................................. 36
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3 3
RESET ..................................................................................................................................................... 37 3.1 3.2 3.3 3.4 OVERVIEW..................................................................................................................................... 37 POWER ON RESET......................................................................................................................... 38 WATCHDOG RESET...................................................................................................................... 38 BROWN OUT RESET ..................................................................................................................... 39 BROWN OUT DESCRIPTION ................................................................................................. 39
3.4.1
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION........................................................ 40 3.4.3 BROWN OUT RESET IMPROVEMENT.................................................................................. 40 3.5 EXTERNAL RESET ........................................................................................................................ 43 3.6 EXTERNAL RESET CIRCUIT ....................................................................................................... 43 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 4 4 Simply RC Reset Circuit ........................................................................................................... 43 Diode & RC Reset Circuit ........................................................................................................ 44 Zener Diode Reset Circuit ........................................................................................................ 44 Voltage Bias Reset Circuit........................................................................................................ 45 External Reset IC...................................................................................................................... 46
SYSTEM CLOCK .................................................................................................................................. 47 4.1 4.2 4.3 4.4 OVERVIEW..................................................................................................................................... 47 CLOCK BLOCK DIAGRAM .......................................................................................................... 47 OSCM REGISTER ........................................................................................................................... 48 SYSTEM HIGH CLOCK ................................................................................................................. 49
4.4.1 INTERNAL HIGH RC............................................................................................................... 49 4.4.2 EXTERNAL HIGH CLOCK...................................................................................................... 49 4.4.2.1 CRYSTAL/CERAMIC......................................................................................................... 50 4.4.2.2 RC......................................................................................................................................... 50 4.4.2.3 EXTERNAL CLOCK SIGNAL........................................................................................... 51 4.5 SYSTEM LOW CLOCK .................................................................................................................. 52 4.5.1 5 5 SYSTEM CLOCK MEASUREMENT ........................................................................................ 53
SYSTEM OPERATION MODE ........................................................................................................... 54 5.1 5.2 5.3 OVERVIEW..................................................................................................................................... 54 SYSTEM MODE SWITCHING EXAMPLE ................................................................................... 55 WAKEUP ......................................................................................................................................... 57 OVERVIEW .............................................................................................................................. 57 WAKEUP TIME........................................................................................................................ 57 P1W WAKEUP CONTROL REGISTER ................................................................................... 57
5.3.1 5.3.2 5.3.3 6 6
INTERRUPT........................................................................................................................................... 58 6.1 6.2 OVERVIEW..................................................................................................................................... 58 INTEN INTERRUPT ENABLE REGISTER................................................................................... 59
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Preliminary Version 0.3
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8-Bit Micro-Controller
6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 7
INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 60 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 60 PUSH, POP ROUTINE .................................................................................................................... 61 INT0 (P0.0) INTERRUPT OPERATION......................................................................................... 62 INT1 (P0.1) INTERRUPT OPERATION......................................................................................... 64 T0 INTERRUPT OPERATION ....................................................................................................... 65 TC1 INTERRUPT OPERATION..................................................................................................... 67 MULTI-INTERRUPT OPERATION............................................................................................... 68
I/O PORT ................................................................................................................................................ 69 7.1 7.2 7.3 7.4 7.5 I/O PORT MODE ............................................................................................................................. 69 I/O PULL UP REGISTER ................................................................................................................ 70 I/O OPEN-DRAIN REGISTER........................................................................................................ 71 I/O PORT DATA REGISTER .......................................................................................................... 72 PORT1, PORT2 APPLICATION CIRCUIT .................................................................................... 73
8 8
TIMERS .................................................................................................................................................. 74 8.1 8.2 WATCHDOG TIMER...................................................................................................................... 74 TIMER 0 (T0) ................................................................................................................................... 76
8.2.1 OVERVIEW .............................................................................................................................. 76 8.2.2 T0M MODE REGISTER........................................................................................................... 77 8.2.3 T0C COUNTING REGISTER................................................................................................... 78 8.2.4 T0 TIMER OPERATION SEQUENCE ..................................................................................... 79 8.3 TIMER/COUNTER 0 (TC1) ............................................................................................................ 80 8.3.1 OVERVIEW .............................................................................................................................. 80 8.3.2 TC1M MODE REGISTER ........................................................................................................ 81 8.3.3 TC1C COUNTING REGISTER ................................................................................................ 82 8.3.4 TC1R AUTO-LOAD REGISTER .............................................................................................. 83 8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER) .................................................................. 84 8.3.6 TC1 TIMER OPERATION SEQUENCE .................................................................................. 85 8.4 PWM1 MODE .................................................................................................................................. 86 8.4.1 8.4.2 8.4.3 8.4.4 9 9 10 10 10.1 10.2 OVERVIEW .............................................................................................................................. 86 TCxIRQ and PWM Duty ........................................................................................................... 87 PWM Duty with TCxR Changing.............................................................................................. 88 PWM PROGRAM EXAMPLE .................................................................................................. 89
INSTRUCTION TABLE ....................................................................................................................... 90 ELECTRICAL CHARACTERISTIC .............................................................................................. 91 ABSOLUTE MAXIMUM RATING ................................................................................................ 91 ELECTRICAL CHARACTERISTIC............................................................................................... 91
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8-Bit Micro-Controller
11 11 11.1 11.2 12 12 12.1 12.2 12.3 13 13 13.1 13.2 13.3 13.4
OTP PROGRAMMING PIN............................................................................................................. 92 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET: .............................................. 92 PROGRAMMING PIN MAPPING: .......................................................................................................... 93 PACKAGE INFORMATION ........................................................................................................... 94 SK-DIP 28 PIN ................................................................................................................................. 94 SOP 28 PIN....................................................................................................................................... 95 SSOP 28 PIN..................................................................................................................................... 96 MARKING DEFINITION................................................................................................................. 97 INTRODUCTION ............................................................................................................................ 97 MARKING INDETIFICATION SYSTEM...................................................................................... 97 MARKING EXAMPLE ................................................................................................................... 98 DATECODE SYSTEM .................................................................................................................... 98
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1
PRODUCT OVERVIEW
SN8P2614 is a 28 pin general purpose MCU with internal high RC 16MHz and 200mA sink current @VSS+1.5V of Port 2. The combination of Port 1 and Port 2 is for LED panel scan with large current design. Internal high RC 16MHz provides more I/O pin and low cost high clock oscillator selection. SN8P2614 has unique pin assignment not compatible with SN8P2604 or SN8P2604A. The system is base on 4T design for high noisy application, e.g. household products...
1.1 FEATURES
Memory configuration OTP ROM size: 6K * 16 bits. RAM size: 192 * 8 bits. 8 levels stack buffer I/O pin configuration Bi-directional: P0, P1, P2, P5. Wakeup: P0, P1 level change trigger. Pull-up resisters: P0, P1, P2, P5. External Interrupt trigger edge: P0.0 controlled by PEDGE register. P0.1 is falling edge trigger only. Each of P2 sink current: 200mA @VSS+1.5V. 3-Level LVD. Reset system and power monitor. Four interrupt sources Two internal interrupts: T0, TC1. One external interrupts: INT0, INT1. Powerful instructions Four clocks per instruction cycle (4T) One instruction's length is one word. Most of instructions are one cycle only. All ROM area JMP instruction. All ROM area CALL address instruction. All ROM area lookup table function (MOVC) Two 8-bit Timer/Counter T0: Basic timer TC1: Auto-reload timer/Counter/PWM/Buzzer output One channel PWM output. (PWM1). One channel Buzzer output. (BZ1). On chip watchdog timer and clock source is internal low clock RC type (16KHz @3V, 32KHz @5V). Four system clocks External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal high clock: 16MHz RC type. Internal low clock: RC type 16KHz(3V), 32KHz(5V) Four operating modes Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Green mode: Periodical wakeup by T0 Timer Package (Chip form support) SK-DIP 28 pins SOP 28 pins. SSOP 28 pins.

Features Selection Table CHIP ROM RAM Stack 8 8 8 Timer System LVD PWM Wakeup I/O IHRC Clock LVD_L LVD_M LVD_H BZ No. T0 TC1 V V V V V V 24 24 26 V 1T 1T 4T 1.8V 2.0V 2.0V 2.4V 2.4V 3.6V 3.6V 1-ch 1-ch 1-ch 11 11 13 Package SK-DIP28/SOP28/ SSOP28 SK-DIP28/SOP28/ SSOP28 SK-DIP28/SOP28/ SSOP28
SN8P2604 4K*16 128 SN8P2604A 4K*16 128 SN8P2614 6K*16 192
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1.2 SYSTEM BLOCK DIAGRAM
INTERNAL HIGH RC OTP IR ROM FLAGS TIMING GENERATOR EXTERNAL HIGH OSC. INTERNAL LOW RC LVD (Low Voltage Detector) WATCHDOG TIMER
PC
ALU RAM PWM 1 PWM1
ACC INTERRUPT CONTROL
SYSTEM REGISTERS
BUZZER 1
BUZZER1
TIMER & COUNTER
P0
P1
P2
P5
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8-Bit Micro-Controller
1.3 PIN ASSIGNMENT
SN8P2614K (SK-DIP 28 pins) SN8P2614S (SOP 28 pins) SN8P2614X (SSOP 28 pins)
P5.0 P5.1 P5.2 P5.3/BZ1/PWM1 P5.4 VDD P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
1 U 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 SN8P2614K SN8P2614S SN8P2614X
P0.1/INT1 P0.0/INT0 P0.2/RST/VPP XIN/P0.3 XOUT/P0.4 VSS P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
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8-Bit Micro-Controller
1.4 PIN DESCRIPTIONS
PIN NAME
VDD, VSS P0.0/INT0
TYPE
P I/O
DESCRIPTION
Power supply input pins for digital circuit. Port 0.0 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. Built-in wakeup function. INT0 trigger pin (Schmitt trigger). Port 0.1 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. Built-in wakeup function. INT1 trigger pin (Schmitt trigger). TC1 event counter clock input pin. P0.2: Input only pin (Schmitt trigger) if disable external reset function. P0.2 without build-in pull-up resister. P0.2 is input only pin without pull-up resistor under P0.2 mode. Add the 100 ohm external resistor on P0.2, when it is set to be input pin. Built-in wakeup function. RST: System reset input pin. Schmitt trigger structure, low active, normal stay to "high". VPP: OTP programming pin. XIN: Oscillator input pin while external oscillator enable (crystal and RC). P0.3: Port 0.3 bi-direction pin under internal 16M RC. Schmitt trigger structure and built-in pull-up resisters as input mode. Built wakeup function. XOUT: Oscillator output pin while external crystal enable. P0.4: Port 0.4 bi-direction pin under internal 16M RC and external RC. Schmitt trigger structure and built-in pull-up resisters as input mode. Built wakeup function. P1[1:0]: Port 1.0, P1.1 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. Open-Drain function controlled by "P1OC" register. Built wakeup function. P1: Port 1 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. Built wakeup function. P2: Port 2 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. P5: Port 5 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. Port 5.4 bi-direction pin. Schmitt trigger structure and built-in pull-up resisters as input mode. TC0 / 2 signal output pin for buzzer or PWM0 output pin.
P0.1/INT1
I/O
P0.2/RST/VPP
I, P
P0.3/XIN
I/O
P0.4/XOUT
I/O
P1[1:0]
I/O
P1[7:2] P2[7:0] P5[4:0] P5.3/BZ1/PWM1
I/O I/O I/O I/O
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1.5 PIN CIRCUIT DIAGRAMS
Port 0, 1, 2, 5 structure:
Pull-Up PnM
PnM, PnUR Input Bus
Pin Output Latch
Output Bus
Port 1.0, 1.1 structure:
Pull-Up PnM
PnM, PnUR Input Bus
Pin Output Latch Open-Drain P1OC
Output Bus
Port 0.3, 0.4 structure:
Pull-Up Oscillator Code Option PnM
PnM, PnUR Input Bus
Pin Output Latch Output Bus
Int. Osc.
Port 0.2 structure:
Ext. Reset Code Option Int. Bus Int. Rst
Pin
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8-Bit Micro-Controller
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
6K words ROM ROM 0000H 0001H . . 0007H 0008H 0009H . . 000FH 0010H 0011H . . . . . 17FCH 17FDH 17FEH 17FFH Reset vector General purpose area Interrupt vector User interrupt vector User program User reset vector Jump to user start address
General purpose area
End of user program Reserved
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2.1.1.1
RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset. Power On Reset (NT0=1, NPD=0). Watchdog Reset (NT0=0, NPD=0). External Reset (NT0=1, NPD=1). After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD flags of PFLAG register. The following example shows the way to define the reset vector in the program memory. Example: Defining Reset Vector ORG JMP ... ORG START: ... ... 0 START ; 0000H ; Jump to user program address.
10H ; 0010H, The head of user program. ; User program
ENDP
; End of program
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2.1.1.2
INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Note: "PUSH", "POP" instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8. .CODE ORG JMP ... ORG PUSH ... ... POP RETI ... START: ... ... JMP ... ENDP START 0 START ; 0000H ; Jump to user program address.
8
; Interrupt vector. ; Save ACC and PFLAG register to buffers.
; Load ACC and PFLAG register from buffers. ; End of interrupt service routine ; The head of user program. ; User program ; End of user program ; End of program
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Example: Defining Interrupt Vector. The interrupt service routine is following user program. .CODE ORG JMP ... ORG JMP ORG START: ... ... ... JMP ... MY_IRQ: PUSH ... ... POP RETI ... ENDP 0 START 8 MY_IRQ 10H ; 0010H, The head of user program. ; User program. START ; End of user program. ;The head of interrupt service routine. ; Save ACC and PFLAG register to buffers. ; 0000H ; Jump to user program address. ; Interrupt vector. ; 0008H, Jump to interrupt service routine address.
; Load ACC and PFLAG register from buffers. ; End of interrupt service routine. ; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a "JMP" instruction to make the program starts from the beginning. 2. The address 0008H is interrupt vector. 3. User's program is a loop routine for main purpose application.
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2.1.1.3
LOOK-UP TABLE DESCRIPTION
In the ROM's data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located "TABLE1". B0MOV B0MOV MOVC Y, #TABLE1$M Z, #TABLE1$L ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; Increment the index address for next address. ; Z+1 ; Z is not overflow. ; Z overflow (FFH 00), Y=Y+1 ; ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data.
INCMS JMP INCMS NOP @@: TABLE1: MOVC ... DW DW DW ...
Z @F Y
0035H 5105H 2012H
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically.
Example: INC_YZ macro. INC_YZ MACRO INCMS JMP INCMS NOP @@: ENDM Z @F Y ; Z+1 ; Not overflow ; Y+1 ; Not overflow
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Example: Modify above example by "INC_YZ" macro. B0MOV B0MOV MOVC INC_YZ @@: TABLE1: MOVC ... DW DW DW ... Y, #TABLE1$M Z, #TABLE1$L ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; Increment the index address for next address. ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data.
0035H 5105H 2012H
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if "carry" happen. Example: Increase Y and Z register by B0ADD/ADD instruction. B0MOV B0MOV B0MOV B0ADD B0BTS1 JMP INCMS NOP GETDATA: MOVC ... TABLE1: DW DW DW ... 0035H 5105H 2012H ; To define a word (16 bits) data. Y, #TABLE1$M Z, #TABLE1$L A, BUF Z, A FC GETDATA Y ; To set lookup table's middle address. ; To set lookup table's low address. ; Z = Z + BUF.
; Check the carry flag. ; FC = 0 ; FC = 1. Y+1. ; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012
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2.1.1.4
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter (PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the value of the accumulator (A). Note: PCH only support PC up counting result and doesn't support PC down counting. When PCL is carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL-ACC, PCH keeps value and not change.
Example: Jump table. ORG B0ADD JMP JMP JMP JMP 0X0100 PCL, A A0POINT A1POINT A2POINT A3POINT ; The jump table is from the head of the ROM boundary ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. Example: If "jump table" crosses over ROM boundary will cause errors. @JMP_A MACRO IF JMP ORG ENDIF ADD ENDM VAL (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A
Note: "VAL" is the number of the jump table listing number.
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Example: "@JMP_A" application in SONIX macro file called "MACRO3.H". B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the "@JMP_A" macro will adjust the jump table routine begin from next RAM boundary (0x0100). Example: "@JMP_A" operation.
; Before compiling program. ROM address 0X00FD 0X00FE 0X00FF 0X0100 0X0101 B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT
; After compiling program. ROM address 0X0100 0X0101 0X0102 0X0103 0X0104 B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT
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2.1.1.5
CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the Checksum value. Example: The demo program shows how to calculated Checksum from 00H to the end of user's code. MOV B0MOV MOV B0MOV CLR CLR @@: MOVC B0BSET ADD MOV ADC JMP AAA: INCMS JMP JMP END_CHECK: MOV CMPRS JMP MOV CMPRS JMP JMP Y_ADD_1: INCMS NOP JMP CHECKSUM_END: ... ... END_USER_CODE: ; Label of program end Y @B ; Increase Y ; Jump to checksum calculate A, END_ADDR1 A, Z AAA A, END_ADDR2 A, Y AAA CHECKSUM_END ; Check if Z = low end address ; If Not jump to checksum calculate ; If Yes, check if Y = middle end address ; If Not jump to checksum calculate ; If Yes checksum calculated is done. Z @B Y_ADD_1 ; Z=Z+1 ; If Z != 00H calculate to next address ; If Z = 00H increase Y FC DATA1, A A, R DATA2, A END_CHECK ; Clear C flag ; Add A to Data1 ; Add R to Data2 ; Check if the YZ address = the end of code A,#END_USER_CODE$L END_ADDR1, A ; Save low end address to end_addr1 A,#END_USER_CODE$M END_ADDR2, A ; Save middle end address to end_addr2 Y ; Set Y to 00H Z ; Set Z to 00H
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2.1.2
CODE OPTION TABLE
Content IHRC_16M Function Description High speed internal 16MHz RC. XIN/XOUT become to P0.3/P0.4 bi-direction I/O pins. Low cost RC for external high clock oscillator and XOUT becomes to P0.4 bit-direction I/O pin. High speed crystal /resonator (e.g. 12MHz) for external high clock oscillator. Standard crystal /resonator (e.g. 4M) for external high clock oscillator. Watchdog timer is always on enable even in power down and green mode. Enable watchdog timer. Watchdog timer stops in power down mode and green mode. Disable Watchdog function. Instruction cycle is 4 oscillator clocks. Instruction cycle is 8 oscillator clocks. Instruction cycle is 16 oscillator clocks. Enable External reset pin. Enable P0.2 input only without pull-up resister. Enable ROM code Security function. Disable ROM code Security function. Enable Noise Filter. Disable Noise Filter. LVD will reset chip if VDD is below 2.0V LVD will reset chip if VDD is below 2.0V Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator. LVD will reset chip if VDD is below 2.4V Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.
Code Option
High_Clk
RC 12M X'tal 4M X'tal Always_On
Watch_Dog
Enable Disable Fhosc/4 Fhosc/8 Fhosc/16 Reset P02 Enable Disable Enable Disable LVD_L LVD_M LVD_H
Fcpu Reset_Pin Security Noise_Filter
LVD
Note: 1. In high noisy environment, enable "Noise Filter" and set Watch_Dog as "Always_On"
is strongly recommended. 2. If users define watchdog as "Always_On", assembler will Enable "Watch_Dog" automatically. 3. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock).
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2.1.3 DATA MEMORY (RAM)
192 X 8-bit RAM RAM location
BANK 0
BANK1
Address 000h " " " " " 0FFh 080h " " " " " 0FFh 100h " " 13Fh
General purpose area
80h~FFh of Bank 0 store system registers (128 bytes). System register
End of bank 0 area General purpose area
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2.1.4 SYSTEM REGISTER
2.1.4.1
0 8 9 A B C D E F
L P1W P0 P0UR
SYSTEM REGISTER TABLE
1
H P1M P1 P1UR
2
R P2M P2 P2UR
3
Z -
4
Y -
5
P5M P5 P5UR
6
@HL
7
@YZ
8
P0M INTRQ T0M -
9
INTEN T0C P1OC
A
OSCM -
B
-
C
WDTR TC1M -
D
TC1C -
E
PCL TC1R -
F
PEDGE PCH STKP -
PFLAG RBANK
STK7L STK7H STK6L
STK6H STK5L STK5H STK4L STK4H
STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
2.1.4.2
PFLAG = H, L = P1W = PEDGE = PnM = P1OC = INTRQ = OSCM = T0M = TC1M = TC1R = @HL = STKP =
SYSTEM REGISTER DESCRIPTION
ROM page and special flag register. Working, @HL and ROM addressing register. Port 1 wakeup register. P0.0 edge direction register. Port n input/output mode register. Port 1 open-drain control register. Interrupt request register. Oscillator mode register. T0 mode register. TC1 mode register. TC1 auto-reload data buffer. RAM HL indirect addressing index pointer. Stack pointer buffer. R= RBANK = Y, Z = Pn = PnUR = INTEN = PCH, PCL = T0C = TC1C = WDTR = @YZ = STK0~STK3 = Working register and ROM look-up data buffer. RAM bank selection. Working, @YZ and ROM addressing register. Port n data buffer. Port n pull-up resister control register. Interrupt enable register. Program counter. TC0 counting register. TC1 counting register. Watchdog timer clear register. RAM YZ indirect addressing index pointer. Stack 0 ~ stack 3 buffer.
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2.1.4.3
Address 080H 081H 082H 083H 084H 086H 087H 0B8H 0BFH 0C0H 0C1H 0C2H 0C5H 0C8H 0C9H 0CAH 0CCH 0CEH 0CFH 0D0H 0D1H 0D2H 0D5H 0D8H 0D9H 0DCH 0DDH 0DEH 0DFH 0E0H 0E1H 0E2H 0E5H 0E6H 0E7H 0E9H 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH
BIT DEFINITION of SYSTEM REGISTER
Bit7 LBIT7 HBIT7 RBIT7 ZBIT7 YBIT7 NT0 P17W P17M P27M 0 WDTR7 PC7 P17 P27 T0ENB T0C7 TC1ENB TC1C7 TC1R7 GIE P17UR P27UR @HL7 @YZ7 S7PC7 S6PC7 S5PC7 S4PC7 S3PC7 S2PC7 S1PC7 S0PC7 Bit6 LBIT6 HBIT6 RBIT6 ZBIT6 YBIT6 NPD P16W P16M P26M TC1IRQ TC1IEN 0 WDTR6 PC6 P16 P26 T0rate2 T0C6 TC1rate2 TC1C6 TC1R6 P16UR P26UR @HL6 @YZ6 S7PC6 S6PC6 S5PC6 S4PC6 S3PC6 S2PC6 S1PC6 S0PC6 Bit5 LBIT5 HBIT5 RBIT5 ZBIT5 YBIT5 LVD36 P15W P15M P25M 0 WDTR5 PC5 P15 P25 T0rate1 T0C5 TC1rate1 TC1C5 TC1R5 P15UR P25UR @HL5 @YZ5 S7PC5 S6PC5 S5PC5 S4PC5 S3PC5 S2PC5 S1PC5 S0PC5 Bit4 LBIT4 HBIT4 RBIT4 ZBIT4 YBIT4 LVD24 P04M P00G1 P14W P14M P24M P54M T0IRQ T0IEN CPUM1 WDTR4 PC4 PC12 P04 P14 P24 P54 T0rate0 T0C4 TC1rate0 TC1C4 TC1R4 P04UR P14R P24R P54R @HL4 @YZ4 S7PC4 S7PC12 S6PC4 S6PC12 S5PC4 S5PC12 S4PC4 S4PC12 S3PC4 S3PC12 S2PC4 S2PC12 S1PC4 S1PC12 S0PC4 S0PC12 Bit3 LBIT3 HBIT3 RBIT3 ZBIT3 YBIT3 P03M P00G0 P13W P13M P23M P53M CPUM0 WDTR3 PC3 PC11 P03 P13 P23 P53 T0C3 TC1CKS TC1C3 TC1R3 P03UR P13R P23R P53R @HL3 @YZ3 S7PC3 S7PC11 S6PC3 S6PC11 S5PC3 S5PC11 S4PC3 S4PC11 S3PC3 S3PC11 S2PC3 S2PC11 S1PC3 S1PC11 S0PC3 S0PC11 Bit2 LBIT2 HBIT2 RBIT2 ZBIT2 YBIT2 C P12W P12M P22M P52M CLKMD WDTR2 PC2 PC10 P02 P12 P22 P52 T0C2 ALOAD1 TC1C2 TC1R2 STKPB2 P12R P22R P52R @HL2 @YZ2 S7PC2 S7PC10 S6PC2 S6PC10 S5PC2 S5PC10 S4PC2 S4PC10 S3PC2 S3PC10 S2PC2 S2PC10 S1PC2 S1PC10 S0PC2 S0PC10 Bit1 LBIT1 HBIT1 RBIT1 ZBIT1 YBIT1 DC P01M P11W P11M P21M P51M P01IRQ P01IEN STPHX WDTR1 PC1 PC9 P01 P11 P21 P51 T0C1 TC1OUT TC1C1 TC1R1 STKPB1 P01UR P11R P21R P51R @HL1 @YZ1 P11OC S7PC1 S7PC9 S6PC1 S6PC9 S5PC1 S5PC9 S4PC1 S4PC9 S3PC1 S3PC9 S2PC1 S2PC9 S1PC1 S1PC9 S0PC1 S0PC9 Bit0 LBIT0 HBIT0 RBIT0 ZBIT0 YBIT0 Z RBANKS0 P00M P10W P10M P20M P50M P00IRQ P00IEN 0 WDTR0 PC0 PC8 P00 P10 P20 P50 T0TB T0C0 PWM1OUT TC1C0 TC1R0 STKPB0 P00R P10R P20R P50R @HL0 @YZ0 P10OC S7PC0 S7PC8 S6PC0 S6PC8 S5PC0 S5PC8 S4PC0 S4PC8 S3PC0 S3PC8 S2PC0 S2PC8 S1PC0 S1PC8 S0PC0 S0PC8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W W W W W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Remarks L H R Z Y PFLAG RBANK P0M PEDGE P1W wakeup register P1M I/O direction P2M I/O direction P5M I/O direction INTRQ INTEN OSCM WDTR PCL PCH P0 data buffer P1 data buffer P2 data buffer P5 data buffer T0M T0C TC1M TC1C TC1R STKP stack pointer P0 pull-up register P1 pull-up register P2 pull-up register P5 pull-up register @HL index pointer @YZ index pointer P1OCopen-drain STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
Note:
1. To avoid system error, please be sure to put all the "0" and "1" as it indicates in the above
table. 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with "F" prefix code. 4. "b0bset", "b0bclr", "bset", "bclr" instructions are only available to the "R/W" registers. 5. For detail description, please refer to the "System Register Quick Reference Table".
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2.1.4.4
ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can't be access by "B0MOV" instruction during the instant addressing mode. Example: Read and write ACC value. ; Read ACC data and store in BUF data memory. MOV ; Write a immediate data into ACC. MOV A, #0FH BUF, A
; Write ACC data from BUF data memory. MOV ; or B0MOV A, BUF A, BUF
The system doesn't store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to other data memories. "PUSH", "POP" save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ... ... POP RETI ; Save ACC and PFLAG to buffers. . ; Load ACC and PFLAG from buffers. ; Exit interrupt service vector
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2.1.4.5
PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status. NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD36 bits indicate LVD detecting power voltage status. 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NT0 NPD LVD36 LVD24 C DC Z PFLAG Read/Write R/W R/W R R R/W R/W R/W After reset 0 0 0 0 0 Bit [7:6] NT0, NPD: Reset status flag. NT0 NPD Reset Status 0 0 Watch-dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin LVD36: LVD 3.6V operating flag and only support LVD code option is LVD_H. 0 = Inactive (VDD > 3.6V). 1 = Active (VDD <= 3.6V). LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M. 0 = Inactive (VDD > 2.4V). 1 = Active (VDD <= 2.4V). C: Carry flag 1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic "1", comparison result 0. 0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic "0", comparison result < 0. DC: Decimal carry flag 1 = Addition with carry from low nibble, subtraction without borrow from high nibble. 0 = Addition without carry from low nibble, subtraction with borrow from high nibble. Z: Zero flag 1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags.
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
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2.1.4.6
PROGRAM COUNTER
The program counter (PC) is a 13-bit binary counter separated into the high-byte 5 and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 12. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PC12 PC11 PC10 PC9 0 PCH 0 0 0 Bit 8 PC8 0 Bit 7 PC7 0 Bit 6 PC6 0 Bit 5 PC5 0 Bit 4 PC4 0 PCL Bit 3 PC3 0 Bit 2 PC2 0 Bit 1 PC1 0 Bit 0 PC0 0
PC After reset
ONE ADDRESS SKIPPING There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction. If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction. B0BTS1 JMP ... ... NOP B0MOV B0BTS0 JMP ... ... NOP FC C0STEP ; To skip, if Carry_flag = 1 ; Else jump to C0STEP.
C0STEP:
A, BUF0 FZ C1STEP
; Move BUF0 value to ACC. ; To skip, if Zero flag = 0. ; Else jump to C1STEP.
C1STEP:
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS JMP ... ... NOP A, #12H C0STEP ; To skip, if ACC = 12H. ; Else jump to C0STEP.
C0STEP:
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If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: INCS JMP ... ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero.
C0STEP: INCMS instruction:
C0STEP:
INCMS JMP ... ... NOP
BUF0 C0STEP
; Jump to C0STEP if BUF0 is not zero.
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next instruction. DECS instruction: DECS JMP ... ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero.
C0STEP:
DECMS instruction: DECMS JMP ... ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero.
C0STEP:
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MULTI-ADDRESS JUMPING Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. Program Counter supports "ADD M,A", "ADC M,A" and "B0ADD M,A" instructions for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value by the three instructions and don't care PCL overflow problem. Note: PCH only support PC up counting result and doesn't support PC down counting. When PCL is carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL-ACC, PCH keeps value and not change.
Example: If PC = 0323H (PCH = 03H, PCL = 23H) ; PC = 0323H MOV B0MOV ... ; PC = 0328H MOV B0MOV ... A, #00H PCL, A ; Jump to address 0300H A, #28H PCL, A ; Jump to address 0328H
Example: If PC = 0323H (PCH = 03H, PCL = 23H) ; PC = 0323H B0ADD JMP JMP JMP JMP ... ... PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT
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2.1.4.7
H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers. can be used as general working registers can be used as RAM data pointers with @HL register 081H H Read/Write After reset 080H L Read/Write After reset Bit 7 HBIT7 R/W X Bit 7 LBIT7 R/W X Bit 6 HBIT6 R/W X Bit 6 LBIT6 R/W X Bit 5 HBIT5 R/W X Bit 5 LBIT5 R/W X Bit 4 HBIT4 R/W X Bit 4 LBIT4 R/W X Bit 3 HBIT3 R/W X Bit 3 LBIT3 R/W X Bit 2 HBIT2 R/W X Bit 2 LBIT2 R/W X Bit 1 HBIT1 R/W X Bit 1 LBIT1 R/W X Bit 0 HBIT0 R/W X Bit 0 LBIT0 R/W X
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV H, #00H L, #20H A, @HL ; To set RAM bank 0 for H register ; To set location 20H for L register ; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register. CLR B0MOV CLR_HL_BUF: CLR DECMS JMP CLR END_CLR: ... ... @HL L CLR_HL_BUF @HL ; End of clear general purpose data memory area of bank 0 ; Clear @HL to be zero ; L - 1, if L = 0, finish the routine ; Not zero H L, #07FH ; H = 0, bank 0 ; L = 7FH, the last address of the data memory area
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2.1.4.8
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. can be used as general working registers can be used as RAM data pointers with @YZ register can be used as ROM data pointer with the MOVC instruction for look-up table 084H Y Read/Write After reset 083H Z Read/Write After reset Bit 7 YBIT7 R/W Bit 7 ZBIT7 R/W Bit 6 YBIT6 R/W Bit 6 ZBIT6 R/W Bit 5 YBIT5 R/W Bit 5 ZBIT5 R/W Bit 4 YBIT4 R/W Bit 4 ZBIT4 R/W Bit 3 YBIT3 R/W Bit 3 ZBIT3 R/W Bit 2 YBIT2 R/W Bit 2 ZBIT2 R/W Bit 1 YBIT1 R/W Bit 1 ZBIT1 R/W Bit 0 YBIT0 R/W Bit 0 ZBIT0 R/W -
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0. B0MOV B0MOV B0MOV Y, #00H Z, #25H A, @YZ ; To set RAM bank 0 for Y register ; To set location 25H for Z register ; To read a data into ACC
Example: Uses the Y, Z register as data pointer to clear the RAM data. B0MOV B0MOV CLR_YZ_BUF: CLR DECMS JMP CLR END_CLR: ... @YZ Z CLR_YZ_BUF @YZ ; End of clear general purpose data memory area of bank 0 ; Clear @YZ to be zero ; Z - 1, if Z= 0, finish the routine ; Not zero Y, #0 Z, #07FH ; Y = 0, bank 0 ; Z = 7FH, the last address of the data memory area
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2.1.4.9
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register. Can be used as working register For store high-byte data of look-up table (MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the low-byte data will be stored in ACC). 082H R Read/Write After reset Bit 7 RBIT7 R/W Bit 6 RBIT6 R/W Bit 5 RBIT5 R/W Bit 4 RBIT4 R/W Bit 3 RBIT3 R/W Bit 2 RBIT2 R/W Bit 1 RBIT1 R/W Bit 0 RBIT0 R/W -
Note: Please refer to the "LOOK-UP TABLE DESCRIPTION" about R register look-up table application.
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2.2 ADDRESSING MODE
2.2.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
Example: Move the immediate data 12H to ACC. MOV A, #12H ; To set an immediate data 12H into ACC.
Example: Move the immediate data 12H to R register. B0MOV R, #12H ; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.2.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
Example: Move 0x12 RAM location data into ACC. B0MOV A, 12H ; To get a content of RAM location 0x12 of bank 0 and save in ACC.
Example: Move ACC data into 0x12 RAM location. B0MOV 12H, A ; To get a content of ACC and save in RAM location 12H of bank 0.
2.2.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z). Example: Indirectly addressing mode with @HL register B0MOV B0MOV B0MOV H, #0 L, #12H A, @HL ; To clear H register to access RAM bank 0. ; To set an immediate data 12H into L register. ; Use data pointer @HL reads a data from RAM location ; 012H into ACC.
Example: Indirectly addressing mode with @YZ register B0MOV B0MOV B0MOV Y, #0 Z, #12H A, @YZ ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.
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2.3 STACK OPERATION
2.3.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter's (PC) data when interrupt service routine and "CALL" instruction are executed. The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program counter (PC) data.
RET / RETI CALL / INTERRUPT
PCH
PCL
STACK Level STKP + 1 STKP - 1 STKP = 7 STKP = 6 STKP = 5 STKP STKP = 4 STKP = 3 STKP = 2 STKP = 1 STKP = 0
STACK Buffer High Byte STK7H STK6H STK5H STKP STK4H STK3H STK2H STK1H STK0H
STACK Buffer Low Byte STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L
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2.3.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 13-bit data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to the top address of stack buffer and write the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0. 0DFH STKP Read/Write After reset Bit[2:0] Bit 7 Bit 7 GIE R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 STKPB2 R/W 1 Bit 1 STKPB1 R/W 1 Bit 0 STKPB0 R/W 1
STKPBn: Stack pointer (n = 0 ~ 2) GIE: Global interrupt control bit. 0 = Disable. 1 = Enable. Please refer to the interrupt chapter.
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the beginning of the program. MOV B0MOV A, #00000111B STKP, A
0F0H~0FFH STKnH Read/Write After reset 0F0H~0FFH STKnL Read/Write After reset
Bit 7 Bit 7 SnPC7 R/W 0
Bit 6 Bit 6 SnPC6 R/W 0
Bit 5 Bit 5 SnPC5 R/W 0
Bit 4 SnPC12 R/W 0 Bit 4 SnPC4 R/W 0
Bit 3 SnPC11 R/W 0 Bit 3 SnPC3 R/W 0
Bit 2 SnPC10 R/W 0 Bit 2 SnPC2 R/W 0
Bit 1 SnPC9 R/W 0 Bit 1 SnPC1 R/W 0
Bit 0 SnPC8 R/W 0 Bit 0 SnPC0 R/W 0
STKn = STKnH , STKnL (n = 7 ~ 0)
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2.3.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC) to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as the following table. STKP Register STKPB1 STKPB0
1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0
Stack Level 0 1 2 3 4 5 6 7 8 >8
STKPB2
1 1 1 1 0 0 0 0 1 1
Stack Buffer High Byte Low Byte
Free STK0H STK1H STK2H STK3H STK4H STK5H STK6H STK7H Free STK0L STK1L STK2L STK3L STK4L STK5L STK6L STK7L -
Description Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as the following table. STKP Register STKPB2 STKPB1 STKPB0
1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
Stack Level 8 7 6 5 4 3 2 1 0
Stack Buffer High Byte Low Byte
STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H Free STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L Free
Description -
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3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following. Power on reset Watchdog reset Brown out reset External reset (only supports external reset pin enable situation) When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program. 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NT0 NPD LVD36 LVD24 C DC Z PFLAG Read/Write R/W R/W R R R/W R/W R/W After reset 0 0 0 0 0 Bit [7:6] NT0, NPD: Reset status flag. NT0 NPD Condition 0 0 Watchdog reset 0 1 Reserved 1 0 Power on reset and LVD reset. 1 1 External reset
Description Watchdog timer overflow. Power voltage is lower than LVD detecting level. External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of different oscillator is not fixed. RC type oscillator's start-up time is very short, but the crystal type is longer. Under client terminal application, users have to take care the power on reset time for the master terminal requirement. The reset timing diagram is as following.
VDD
LVD Detect Level
Power
VSS
VDD
External Reset
VSS External Reset Low Detect Watchdog Normal Run
External Reset High Detect Watchdog Overflow
Watchdog Reset
Watchdog Stop
System Normal Run
System Status
System Stop Power On Delay Time External Reset Delay Time Watchdog Reset Delay Time
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3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising curve and needs some time to achieve the normal voltage. Power on reset sequence is as following. Power-up: System detects the power voltage up and waits for power stable. External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is not high level, the system keeps reset status and waits external reset pin released. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program. Under error condition, system is in unknown situation and watchdog can't be clear by program before watchdog timer overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and returns normal mode. Watchdog reset sequence is as following. Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the system is reset. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. Watchdog timer application note is as following. Before clearing watchdog timer, check I/O status and check RAM contents can improve system error. Don't clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail. Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the "WATCHDOG TIMER" about watchdog timer detail information.
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3.4 BROWN OUT RESET
3.4.1 BROWN OUT DESCRIPTION
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error. VDD
System Work Well Area V1 System Work Error Area
V2 VSS
V3
Brown Out Reset Diagram The power dropping might through the voltage range that's the system dead-band. The dead-band means the power range can't offer the system minimum operation power requirement. The above diagram is a typical brown out reset diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate the system working area. The above area is the system work well area. The below area is the system work error area called dead-band. V1 doesn't touch the below area and not effect the system operation. But the V2 and V3 is under the below area and may induce the system error occurrence. Let system under dead-band includes some conditions. DC application: The power source of DC application is usually using battery. When low battery condition and MCU drive any loading, the power drops and keeps in dead-band. Under the situation, the power won't drop deeper and not touch the system reset voltage. That makes the system under dead-band. AC application: In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power situation. The power on duration and power down duration are longer in AC application. The system power on sequence protects the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while.
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3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. Different system executing rates have different system minimum operating voltage. The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini. Operating Voltage.
Vdd (V)
Normal Operating Area
Dead-Band Area Reset Area System Rate (Fcpu)
System Reset Voltage.
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system reset voltage.
3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following. LVD reset Watchdog reset Reduce the system executing rate External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC) Note: 1. The " Zener diode reset circuit", "Voltage bias reset circuit" and "External reset IC" can completely improve the brown out reset, DC low battery and AC slow power down conditions. 2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (" Zener diode reset circuit", "Voltage bias reset circuit", "External reset IC"). The structure can improve noise effective and get good EFT characteristic.
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LVD reset:
VDD
LVD Detect Voltage
Power
VSS Power is below LVD Detect Voltage and System Reset.
System Normal Run
System Status
System Stop Power On Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to improve brown out reset is depend on application requirement and environment. If the power variation is very deep, violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and make system work error, the LVD can't be the protection and need to other reset methods. More detail LVD information is in the electrical characteristic section. The LVD is three levels design (2.0V/2.4V/3.6V) and controlled by LVD code option. The 2.0V LVD is always enable for power on reset and Brown Out reset. The 2.4V LVD includes LVD reset function and flag function to indicate VDD status function. The 3.6V includes flag function to indicate VDD status. LVD flag function can be an easy low battery detector. LVD24, LVD36 flags indicate VDD voltage level. For low battery detect application, only checking LVD24, LVD36 status to be battery status. This is a cheap and easy solution. 086H PFLAG Read/Write After reset Bit 5 Bit 7 NT0 R/W Bit 6 NPD R/W Bit 5 LVD36 R 0 Bit 4 LVD24 R 0 Bit 3 Bit 2 C R/W 0 Bit 1 DC R/W 0 Bit 0 Z R/W 0
LVD36: LVD 3.6V operating flag and only support LVD code option is LVD_H. 0 = Inactive (VDD > 3.6V). 1 = Active (VDD <= 3.6V). LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M. 0 = Inactive (VDD > 2.4V). 1 = Active (VDD <= 2.4V).
Bit 4
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LVD 2.0V Reset 2.4V Flag 2.4V Reset 3.6V Flag
LVD_L Available -
LVD Code Option LVD_M Available Available -
LVD_H Available Available Available
LVD_L If VDD < 2.0V, system will be reset. Disable LVD24 and LVD36 bit of PFLAG register LVD_M If VDD < 2.0V, system will be reset. Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is "0". If VDD <= 2.4V, LVD24 flag is "1" Disable LVD36 bit of PFLAG register LVD2_H If VDD < 2.4V, system will be reset. Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is "0". If VDD <= 2.4V, LVD24 flag is "1" Enable LVD36 bit of PFLAG register. If VDD > 3.6V, LVD36 is "0". If VDD <= 3.6V, LVD36 flag is "1" Note: 1. After any LVD reset, LVD24, LVD36 flags are cleared. 2. The voltage level of LVD 2.4V or 3.6V is for design reference only. Don't use the LVD indicator as precision VDD measurement.
Watchdog reset: The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear at one point of program. Don't clear the watchdog timer in several addresses. The system executes normally and the watchdog won't reset system. When the system is under dead-band and the execution error, the watchdog timer can't be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method also can improve brown out reset condition and make sure the system to return normal mode. If the system reset by watchdog and the power is still in dead-band, the system reset sequence won't be successful and the system stays in reset status until the power return to normal range. Watchdog timer application note is as following. Reduce the system executing rate: If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band. The lower system rate is with lower minimum operating voltage. Select the power voltage that's no dead-band issue and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue. This way needs to modify whole program timing to fit the application requirement. External reset circuit: The external reset methods also can improve brown out reset and is the complete solution. There are three external reset circuits to improve brown out reset including "Zener diode reset circuit", "Voltage bias reset circuit" and "External reset IC". These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section.
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3.5 EXTERNAL RESET
External reset function is controlled by "Reset_Pin" code option. Set the code option as "Reset" option to enable external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in power on and normal running mode. During system power-up, the external reset pin must be high level input, or the system keeps in reset status. External reset sequence is as following. External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is not high level, the system keeps reset status and waits external reset pin released. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. The external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in AC power application...
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
VDD R1 47K ohm R2 100 ohm C1 0.1uF VSS
RST
MCU
VCC
GND
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset.
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3.6.2 Diode & RC Reset Circuit
VDD DIODE R1 47K ohm R2 100 ohm C1 0.1uF VSS
RST
MCU
VCC
GND
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal. The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can improve slight brown out reset condition. Note: The R2 100 ohm resistor of "Simply reset circuit" and "Diode & RC reset circuit" is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
VDD R1 33K ohm E R2 B C Q1
RST
10K ohm Vz
MCU
R3 40K ohm VSS
VCC
GND
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely. Use zener voltage to be the active level. When VDD voltage level is above "Vz + 0.7V", the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below "Vz + 0.7V", the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application.
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3.6.4 Voltage Bias Reset Circuit
VDD R1 47K ohm B C R2 10K ohm R3 2K ohm VSS E Q1
RST
MCU
VCC
GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely. The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When VDD voltage level is above or equal to "0.7V x (R1 + R2) / R1", the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below "0.7V x (R1 + R2) / R1", the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the circuit diagram condition, the MCU's reset pin level varies with VDD voltage variation, and the differential voltage is 0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power system, the current must be considered to whole system power consumption. Note: Under unstable power condition as brown out reset, "Zener diode rest circuit" and "Voltage bias reset circuit" can protects system no any error occurrence as power dropping. When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation.
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3.6.5 External Reset IC
VDD Bypass Capacitor 0.1uF RST
RST
VDD
Reset IC VSS
MCU
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation.
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4
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is generated from the external oscillator circuit or on-chip 16MHz high-speed RC oscillator circuit (IHRC 16MHz). The low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16KHz @3V, 32KHz @5V). Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is divided by 4 to be the instruction cycle (Fcpu). Fcpu = Fhosc / N, N = 4 ~ 16, Select N by Fcpu code option. Fcpu = Flosc/4.
Normal Mode (High Clock): Slow Mode (Low Clock):
SONIX provides a "Noise Filter" controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well.
4.2 CLOCK BLOCK DIAGRAM
STPHX HOSC CLKMD Fosc Fhosc. Fcpu = Fhosc/4 ~ Fhosc/16 Fcpu Fosc CPUM[1:0]
Fcpu Code Option
XIN XOUT
Flosc.
Fcpu = Flosc/4
HOSC: High_Clk code option. Fhosc: External high-speed clock / Internal high-speed RC clock. Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V). Fosc: System clock source. Fcpu: Instruction cycle.
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4.3 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode. 0CAH OSCM Read/Write After reset Bit 1 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 CPUM1 R/W 0 Bit 3 CPUM0 R/W 0 Bit 2 CLKMD R/W 0 Bit 1 STPHX R/W 0 Bit 0 0 -
STPHX: External high-speed oscillator control bit. 0 = External high-speed oscillator free run. 1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running. CLKMD: System high/Low clock mode control bit. 0 = Normal (dual) mode. System clock is high clock. 1 = Slow mode. System clock is internal low clock. CPUM[1:0]: CPU operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved.
Bit 2
Bit[4:3]
Example: Stop high-speed oscillator B0BSET FSTPHX ; To stop external high-speed oscillator only.
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).
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4.4 SYSTEM HIGH CLOCK
The system high clock is from internal 16MHz oscillator RC type or external oscillator. The high clock type is controlled by "High_Clk" code option. High_Clk Code Option IHRC_16M IHRC_RTC RC 32K 12M 4M Description The high clock is internal 16MHz oscillator RC type. XIN and XOUT pins are general purpose I/O pins. The high clock is internal 16MHz oscillator RC type. XIN and XOUT pins connect with 32768Hz crystal for RTC clock source. The high clock is external RC type oscillator. XOUT pin is general purpose I/O pin. The high clock is external 32768Hz low speed oscillator. The high clock is external high speed oscillator. The typical frequency is 12MHz. The high clock is external oscillator. The typical frequency is 4MHz.
4.4.1 INTERNAL HIGH RC
The chip is built-in RC type internal high clock (16MHz) controlled by "IHRC_16M" or "IHRC_RTC" code options. In "IHRC_16M" mode, the system clock is from internal 16MHz RC type oscillator and XIN / XOUT pins are general-purpose I/O pins. In "IHRC_RTC" mode, the system clock is from internal 16MHz RC type oscillator and XIN / XOUT pins are connected with external 32768 crystal for real time clock (RTC). IHRC: High clock is internal 16MHz oscillator RC type. XIN/XOUT pins are general purpose I/O pins. IHRC_RTC: High clock is internal 16MHz oscillator RC type. XIN/XOUT pins are connected with external 32768Hz crystal/ceramic oscillator for RTC clock source. The RTC period is controlled by OPTION register and RTC timer is T0. Please consult "T0 Timer" chapter to apply RTC function.
4.4.2 EXTERNAL HIGH CLOCK
External high clock includes three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator's start-up time is very short, but the crystal's is longer. The oscillator start-up time decides reset time length.
4MHz Crystal RC
32768Hz Crystal
4MHz Ceramic
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4.4.2.1
CRYSTAL/CERAMIC
Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are different. High_Clk code option supports different frequencies. 12M option is for high speed (ex. 12MHz). 4M option is for normal speed (ex. 4MHz). 32K option is for low speed (ex. 32768Hz).
XIN CRYSTAL C 20pF C 20pF
XOUT
MCU
VDD VSS VCC GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of micro-controller.
4.4.2.2
RC
Selecting RC oscillator is by RC option of High_Clk code option. RC type oscillator's frequency is up to 10MHz. Using "R" value is to change frequency. 50P~100P is good value for "C". XOUT pin is general purpose I/O pin.
XOUT
XIN R
VDD VSS
C
MCU
VCC GND
Note: Connect the R and C as near as possible to the VDD pin of micro-controller.
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4.4.2.3
EXTERNAL CLOCK SIGNAL
Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock signal is input from XIN pin. XOUT pin is general purpose I/O pin.
External Clock Input
XIN XOUT
MCU
VSS VDD
VCC GND
Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.
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4.5 SYSTEM LOW CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC frequency and voltage is as the following figure.
Internal Low RC Frequency
45.00 40.00
40.80 38.08 35.40 32.52 29.20 25.96 22.24 14.72 10.64 7.52 16.00 17.24 18.88
Freq. (KHz)
35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 2.1 2.5 3 3.1 3.3 3.5 4 4.5 5 5.5 6
ILRC
6.5
7
VDD (V)
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD. Flosc = Internal low RC oscillator (about 16KHz @3V, 32KHz @5V). Slow mode Fcpu = Flosc / 4 There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under low power consumption.
Example: Stop internal low-speed oscillator by power down mode. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can't be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register.
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4.5.1 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is useful in RC mode. Example: Fcpu instruction cycle of external oscillator. B0BSET @@: B0BSET B0BCLR JMP P0.0 P0.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. P0M.0 ; Set P0.0 to be output mode for outputting Fcpu toggle signal.
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency.
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5
SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following. High-speed mode Low-speed mode Power-down mode (Sleep mode) Green mode
Power Down Mode (Sleep Mode)
P0, P1 Wake-up Function Active. External Reset Circuit Active. CPUM1, CPUM0 = 01. CLKMD = 1
Normal Mode
P0, P1 Wake-up Function Active. T0 Timer Time Out. External Reset Circuit Active.
CLKMD = 0
Slow Mode
CPUM1, CPUM0 = 10.
P0, P1 Wake-up Function Active. T0 Timer Time Out.
Green Mode
External Reset Circuit Active.
System Mode Switching Diagram Operating mode description POWER DOWN REMARK (SLEEP) EHOSC Running By STPHX By STPHX Stop IHRC Running By STPHX By STPHX Stop ILRC Running Running Running Stop EHOSC with RTC Running By STPHX Running Stop IHRC with RTC Running By STPHX Stop Stop ILRC with RTC Running Running Stop Stop CPU instruction Executing Executing Stop Stop T0 timer *Active *Active *Active Inactive * Active if T0ENB=1 TC1 timer *Active *Active Inactive Inactive * Active if TC1ENB=1 By Watch_Dog By Watch_Dog By Watch_Dog By Watch_Dog Refer to code option Watchdog timer Code option Code option Code option Code option description Internal interrupt All active All active T0 All inactive External interrupt All active All active All active All inactive P0, P1, T0 P0, P1, Reset Wakeup source Reset MODE NORMAL SLOW GREEN EHOSC: External high clock IHRC: Internal high clock (16M RC oscillator) ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V)
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5.2 SYSTEM MODE SWITCHING EXAMPLE
Example: Switch normal/slow mode to power down (sleep) mode. B0BSET FCPUM0 ; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
Example: Switch normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1, Change the system into slow mode ;To stop external high-speed oscillator for power saving.
Example: Switch slow mode to normal mode (The external high-speed oscillator is still running). B0BCLR FCLKMD ;To set CLKMD = 0
Example: Switch slow mode to normal mode (The external high-speed oscillator stops). If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. B0BCLR MOV B0MOV DECMS JMP B0BCLR FSTPHX A, #27 Z, A Z @B FCLKMD ; Turn on the external high-speed oscillator. ; If VDD = 5V, internal RC=32KHz (typical) will delay ; 0.125ms X 81 = 10.125ms for external clock stable ; ; Change the system back to the normal mode
@@:
Example: Switch normal/slow mode to green mode. B0BSET FCPUM1 ; Set CPUM1 = 1.
Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode.
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Example: Switch normal/slow mode to green mode and enable T0 wake-up function. ; Set T0 timer wakeup function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BCLR B0BCLR B0BSET ; Go into green mode B0BCLR B0BSET FT0IEN FT0ENB A,#20H T0M,A A,#74H T0C,A FT0IEN FT0IRQ FT0ENB FCPUM0 FCPUM1 ; To disable T0 interrupt service ; To disable T0 timer ; ; To set T0 clock = Fcpu / 64 ; To set T0C initial value = 74H (To set T0 interval = 10 ms) ; To disable T0 interrupt service ; To clear T0 interrupt request ; To enable T0 timer ;To set CPUMx = 10
Note: During the green mode with T0 wake-up function, the wakeup pin and T0 wakeup the system back to the last mode. T0 wake-up period is controlled by program.
Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC. ; Set T0 timer wakeup function with 0.5 sec RTC. B0BSET B0BSET ; Go into green mode B0BCLR B0BSET FT0ENB FT0TB FCPUM0 FCPUM1 ; To enable T0 timer ; To enable RTC function ;To set CPUMx = 10
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5.3 WAKEUP
5.3.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn't execute. The wakeup trigger can wake the system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change) and internal trigger (T0 timer overflow). Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change) Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0, P1 level change) and internal trigger (T0 timer overflow).
5.3.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. Note: Wakeup from green mode is no wakeup time because the clock doesn't stop in green mode.
The value of the wakeup time is as the following. The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes into normal mode. The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time
5.3.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register. 0C0H P1W Read/Write After reset Bit[7:0] Bit 7 P17W W 0 Bit 6 P16W W 0 Bit 5 P15W W 0 Bit 4 P14W W 0 Bit 3 P13W W 0 Bit 2 P12W W 0 Bit 1 P11W W 0 Bit 0 P10W W 0
P10W~P17W: Port 1 wakeup function control bits. 0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function.
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6
INTERRUPT
6.1 OVERVIEW
This MCU provides three interrupt sources, including two internal interrupt (T0/TC1) and two external interrupt (INT0, INT1). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to "0" for stopping other interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to "1" to accept the next interrupts' request. All of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable Register
INT0 Trigger INT1 Trigger T0 Time Out TC1 Time Out
P00IRQ
INTRQ 4-Bit Latchs
P01IRQ T0IRQ TC1IRQ
Interrupt Enable Gating
Interrupt Vector Address (0008H) Global Interrupt Request Signal
Note: The GIE bit must enable during all interrupt operation.
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6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. One of the register to be set "1" is to enable the interrupt request function. Once of the interrupt occur, the stack is incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. 0C9H INTEN Read/Write After reset Bit 0 Bit 7 Bit 6 TC1IEN R/W 0 Bit 5 Bit 4 T0IEN R/W 0 Bit 3 Bit 2 Bit 1 P01IEN R/W 0 Bit 0 P00IEN R/W 0
P00IEN: External P0.0 interrupt (INT0) control bit. 0 = Disable INT0 interrupt function. 1 = Enable INT0 interrupt function. P01IEN: External P0.1 interrupt (INT1) control bit. 0 = Disable INT1 interrupt function. 1 = Enable INT1 interrupt function. T0IEN: T0 timer interrupt control bit. 0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. TC1IEN: TC1 timer interrupt control bit. 0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function.
Bit 1
Bit 4
Bit 6
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the interrupt requests occurs, the bit of the INTRQ register would be set "1". The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request.
0C8H INTRQ Read/Write After reset Bit 0
Bit 7 -
Bit 6 TC1IRQ R/W 0
Bit 5 -
Bit 4 T0IRQ R/W 0
Bit 3 -
Bit 2 -
Bit 1 P01IRQ R/W 0
Bit 0 P00IRQ R/W 0
P00IRQ: External P0.0 interrupt (INT0) request flag. 0 = None INT0 interrupt request. 1 = INT0 interrupt request. P01IRQ: External P0.1 interrupt (INT1) request flag. 0 = None INT1 interrupt request. 1 = INT1 interrupt request. T0IRQ: T0 timer interrupt request flag. 0 = None T0 interrupt request. 1 = T0 interrupt request. TC1IRQ: TC1 timer interrupt request flag. 0 = None TC1 interrupt request. 1 = TC1 interrupt request.
Bit 1
Bit 4
Bit 6
6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level. 0DFH STKP Read/Write After reset Bit 7 Bit 7 GIE R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 STKPB2 R/W 1 Bit 1 STKPB1 R/W 1 Bit 0 STKPB0 R/W 1
GIE: Global interrupt control bit. 0 = Disable global interrupt. 1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save ACC, PFLAG data. The chip includes "PUSH", "POP" for in/out interrupt service routine. The two instruction save and load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing. Note: "PUSH", "POP" instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is an unique buffer and only one level.
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. ORG JMP ORG JMP ORG START: ... INT_SERVICE: PUSH ... ... POP RETI ... ENDP ; Save ACC and PFLAG to buffers. 0 START 8 INT_SERVICE 10H
; Load ACC and PFLAG from buffers. ; Exit interrupt service vector
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6.6 INT0 (P0.0) INTERRUPT OPERATION
When the INT0 trigger occurs, the P00IRQ will be set to "1" no matter the P00IEN is enable or disable. If the P00IEN = 1 and the trigger event P00IRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be "1". Moreover, the system won't execute interrupt vector even when the P00IRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. If the interrupt trigger direction is identical with wake-up trigger direction, the INT0 interrupt request flag (INT0IRQ) is latched while system wake-up from power down mode or green mode by P0.0 wake-up trigger. System inserts to interrupt vector (ORG 8) after wake-up immediately.
Note: INT0 interrupt request can be latched by P0.0 wake-up trigger.
Note: The interrupt trigger direction of P0.0 is control by PEDGE register.
0BFH PEDGE Read/Write After reset Bit[4:3]
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 P00G1 R/W 1
Bit 3 P00G0 R/W 0
Bit 2 -
Bit 1 -
Bit 0 -
P00G[1:0]: P0.0 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi-direction (Level change trigger).
Example: Setup INT0 interrupt request and bi-direction edge trigger. MOV B0MOV B0BSET B0BCLR B0BSET A, #18H PEDGE, A FP00IEN FP00IRQ FGIE ; Set INT0 interrupt trigger as bi-direction edge. ; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE
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Example: INT0 interrupt service routine. ORG JMP INT_SERVICE: ... B0BTS1 JMP B0BCLR ... ... EXIT_INT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FP00IRQ EXIT_INT FP00IRQ ; Push routine to save ACC and PFLAG to buffers. ; Check P00IRQ ; P00IRQ = 0, exit interrupt vector ; Reset P00IRQ ; INT0 interrupt service routine 8 INT_SERVICE ; Interrupt vector
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6.7 INT1 (P0.1) INTERRUPT OPERATION
When the INT1 trigger occurs, the P01IRQ will be set to "1" no matter the P01IEN is enable or disable. If the P01IEN = 1 and the trigger event P01IRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the P01IEN = 0 and the trigger event P01IRQ is still set to be "1". Moreover, the system won't execute interrupt vector even when the P01IRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. If the interrupt trigger direction is identical with wake-up trigger direction, the INT1 interrupt request flag (INT1IRQ) is latched while system wake-up from power down mode or green mode by P0.1 wake-up trigger. System inserts to interrupt vector (ORG 8) after wake-up immediately. Note: INT1 interrupt request can be latched by P0.1 wake-up trigger.
Note: The interrupt trigger direction of P0.1 is falling edge.
Example: INT1 interrupt request setup. B0BSET B0BCLR B0BSET FP01IEN FP01IRQ FGIE ; Enable INT1 interrupt service ; Clear INT1 interrupt request flag ; Enable GIE
Example: INT1 interrupt service routine. ORG JMP INT_SERVICE: ... B0BTS1 JMP B0BCLR ... ... EXIT_INT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FP01IRQ EXIT_INT FP01IRQ ; Push routine to save ACC and PFLAG to buffers. ; Check P01IRQ ; P01IRQ = 0, exit interrupt vector ; Reset P01IRQ ; INT1 interrupt service routine 8 INT_SERVICE ; Interrupt vector
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6.8 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to "1" however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be "1" and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: T0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FT0IEN FT0ENB A, #20H T0M, A A, #74H T0C, A FT0IEN FT0IRQ FT0ENB FGIE ; Disable T0 interrupt service ; Disable T0 timer ; ; Set T0 clock = Fcpu / 64 ; Set T0C initial value = 74H ; Set T0 interval = 10 ms ; Enable T0 interrupt service ; Clear T0 interrupt request flag ; Enable T0 timer ; Enable GIE
Example: T0 interrupt service routine as no RTC function. ORG JMP INT_SERVICE: ... B0BTS1 JMP B0BCLR MOV B0MOV ... ... EXIT_INT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FT0IRQ EXIT_INT FT0IRQ A, #74H T0C, A ; Push routine to save ACC and PFLAG to buffers. ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; Reset T0IRQ ; Reset T0C. ; T0 interrupt service routine 8 INT_SERVICE ; Interrupt vector
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Note: 1. In RTC mode, clear T0IRQ must be after 1/2 RTC clock source (32768Hz), or the RTC interval time is error. The delay is about 16us and use T0 interrupt service routine executing time to be the 16us delay time. 2. In RTC mode, don't reset T0C in interrupt service routine.
Example: T0 interrupt service routine with RTC function. ORG JMP INT_SERVICE: ... > 16us B0BTS1 JMP ... ... B0BCLR ... EXIT_INT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FT0IRQ EXIT_INT ; Push routine to save ACC and PFLAG to buffers. ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; T0 interrupt service routine ; The time must be longer than 16us. ; Reset T0IRQ 8 INT_SERVICE ; Interrupt vector
FT0IRQ
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6.9 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to "1" no matter the TC1IEN is enable or disable. If the TC1IEN and the trigger event TC1IRQ is set to be "1". As the result, the system will execute the interrupt vector. If the TC1IEN = 0, the trigger event TC1IRQ is still set to be "1". Moreover, the system won't execute interrupt vector even when the TC1IEN is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. Example: TC1 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC1IEN FTC1ENB A, #20H TC1M, A A, #74H TC1C, A FTC1IEN FTC1IRQ FTC1ENB FGIE ; Disable TC1 interrupt service ; Disable TC1 timer ; ; Set TC1 clock = Fcpu / 64 ; Set TC1C initial value = 74H ; Set TC1 interval = 10 ms ; Enable TC1 interrupt service ; Clear TC1 interrupt request flag ; Enable TC1 timer ; Enable GIE
Example: TC1 interrupt service routine. ORG JMP INT_SERVICE: ... B0BTS1 JMP B0BCLR MOV B0MOV ... ... EXIT_INT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FTC1IRQ EXIT_INT FTC1IRQ A, #74H TC1C, A ; Push routine to save ACC and PFLAG to buffers. ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reset TC1C. ; TC1 interrupt service routine 8 INT_SERVICE ; Interrupt vector
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6.10 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. Nevertheless, the IRQ flag "1" doesn't mean the system will execute the interrupt vector. In addition, which means the IRQ flags can be set "1" by the events without enable the interrupt. Once the event occurs, the IRQ will be logic "1". The IRQ and its trigger event relationship is as the below table. Interrupt Name P00IRQ P01IRQ T0IRQ TC1IRQ Trigger Event Description P0.0 trigger controlled by PEDGE. P0.1 falling edge trigger. T0C overflow. TC1C overflow.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests. Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and interrupt request flag in interrupt routine.
Example: Check the interrupt request under multi-interrupt operation ORG JMP INT_SERVICE: ... INTP00CHK: B0BTS1 JMP B0BTS0 JMP INTP01CHK: B0BTS1 JMP B0BTS0 JMP INTT0CHK: B0BTS1 JMP B0BTS0 JMP INTTC1CHK: B0BTS1 JMP B0BTS0 JMP INT_EXIT: ... RETI ; Pop routine to load ACC and PFLAG from buffers. ; Exit interrupt vector FTC1IEN INT_EXIT FTC1IRQ INTTC1 FT0IEN INTTC1CHK FT0IRQ INTT0 FP01IEN INTT0CHK FP01IRQ INTP01 FP00IEN INTP01CHK FP00IRQ INTP00 ; Push routine to save ACC and PFLAG to buffers. ; Check INT0 interrupt request ; Check P00IEN ; Jump check to next interrupt ; Check P00IRQ ; Jump to INT0 interrupt service routine ; Check INT0 interrupt request ; Check P01IEN ; Jump check to next interrupt ; Check P01IRQ ; Jump to INT1 interrupt service routine ; Check T0 interrupt request ; Check T0IEN ; Jump check to next interrupt ; Check T0IRQ ; Jump to T0 interrupt service routine ; Check TC1 interrupt request ; Check TC1IEN ; Jump to exit of IRQ ; Check TC1IRQ ; Jump to TC1 interrupt service routine 8 INT_SERVICE ; Interrupt vector
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7
0B8H P0M Read/Write After reset 0C1H P1M Read/Write After reset 0C2H P2M Read/Write After reset 0C5H P5M Read/Write After reset Bit[7:0]
I/O PORT
7.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction. Bit 7 Bit 7 P17M R/W 0 Bit 7 P27M R/W 0 Bit 7 Bit 6 Bit 6 P16M R/W 0 Bit 6 P26M R/W 0 Bit 6 Bit 5 Bit 5 P15M R/W 0 Bit 5 P25M R/W 0 Bit 5 Bit 4 P04M R/W 0 Bit 4 P14M R/W 0 Bit 4 P24M R/W 0 Bit 4 P54M R/W 0 Bit 3 P03M R/W 0 Bit 3 P13M R/W 0 Bit 3 P23M R/W 0 Bit 3 P53M R/W 0 Bit 2 Bit 2 P12M R/W 0 Bit 2 P22M R/W 0 Bit 2 P52M R/W 0 Bit 1 P01M R/W 0 Bit 1 P12M R/W 0 Bit 1 P22M R/W 0 Bit 1 P51M R/W 0 Bit 0 P00M R/W 0 Bit 0 P10M R/W 0 Bit 0 P20M R/W 0 Bit 0 P50M R/W 0
PnM[7:0]: Pn mode control bits. (n = 0~5). 0 = Pn is input mode. 1 = Pn is output mode.
Note: 1. Users can program them by bit control instructions (B0BSET, B0BCLR). 2. P0.2 is input only pin, and the P0M.2 keeps "1".
Example: I/O mode selecting CLR CLR CLR MOV B0MOV B0MOV B0MOV B0BCLR B0BSET P0M P1M P5M A, #0FFH P0M, A P1M, A P5M, A P1M.2 P1M.2 ; Set all ports to be input mode.
; Set all ports to be output mode.
; Set P1.2 to be input mode. ; Set P1.2 to be output mode.
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7.2 I/O PULL UP REGISTER
0E0H P0UR Read/Write After reset 0E1H P1UR Read/Write After reset 0E2H P2UR Read/Write After reset 0E5H P5UR Read/Write After reset Bit 7 Bit 7 P17R W 0 Bit 7 P27R W 0 Bit 7 Bit 6 Bit 6 P16R W 0 Bit 6 P26R W 0 Bit 6 Bit 5 Bit 5 P15R W 0 Bit 5 P25R W 0 Bit 5 Bit 4 P04R W 0 Bit 4 P14R W 0 Bit 4 P24R W 0 Bit 4 P54R W 0 Bit 3 P03R W 0 Bit 3 P13R W 0 Bit 3 P23R W 0 Bit 3 P53R W 0 Bit 2 Bit 2 P12R W 0 Bit 2 P22R W 0 Bit 2 P52R W 0 Bit 1 P01R W 0 Bit 1 P11R W 0 Bit 1 P21R W 0 Bit 1 P51R W 0 Bit 0 P00R W 0 Bit 0 P10R W 0 Bit 0 P20R W 0 Bit 0 P50R W 0
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps "1".
Example: I/O Pull up Register MOV B0MOV B0MOV B0MOV A, #0FFH P0UR, A P1UR, A P5UR, A ; Enable Port0, 1, 5 Pull-up register, ;
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7.3 I/O OPEN-DRAIN REGISTER
P1.0 is built-in open-drain function. P1.0 must be set as output mode when enable P1.0 open-drain function. Open-drain external circuit is as following.
MCU1 U
VCC Pull-up Resistor
MCU2 U
Open-drain pin
Open-drain pin
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU's pin.
0E9H P1OC Read/Write After reset Bit 0
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 P11OC W 0
Bit 0 P10OC W 0
P10OC: P1.0 open-drain control bit 0 = Disable open-drain mode 1 = Enable open-drain mode P11OC: P1.1 open-drain control bit 0 = Disable open-drain mode 1 = Enable open-drain mode
Bit 1
Example: Enable P1.0 to open-drain mode and output high. B0BSET B0BSET MOV B0MOV P1.0 P10M A, #01H P1OC, A ; Set P1.0 buffer high. ; Enable P1.0 output mode. ; Enable P1.0 open-drain function.
Note: P1OC is write only register. Setting P10OC must be used "MOV" instructions.
Example: Disable P1.0 to open-drain mode and output low. MOV B0MOV A, #0 P1OC, A ; Disable P1.0 open-drain function.
Note: After disable open-drain function, the pin mode returns to last I/O mode.
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7.4 I/O PORT DATA REGISTER
0D0H P0 Read/Write After reset 0D1H P1 Read/Write After reset 0D2H P2 Read/Write After reset 0D5H P5 Read/Write After reset Bit 7 Bit 7 P17 R/W 0 Bit 7 P27 R/W 0 Bit 7 Bit 6 Bit 6 P16 R/W 0 Bit 6 P26 R/W 0 Bit 6 Bit 5 Bit 5 P15 R/W 0 Bit 5 P25 R/W 0 Bit 5 Bit 4 P04 R/W 0 Bit 4 P14 R/W 0 Bit 4 P24 R/W 0 Bit 4 P54 R/W 0 Bit 3 P03 R/W 0 Bit 3 P13 R/W 0 Bit 3 P23 R/W 0 Bit 3 P53 R/W 0 Bit 2 P02 R 0 Bit 2 P12 R/W 0 Bit 2 P22 R/W 0 Bit 2 P52 R/W 0 Bit 1 P01 R/W 0 Bit 1 P11 R/W 0 Bit 1 P21 R/W 0 Bit 1 P51 R/W 0 Bit 0 P00 R/W 0 Bit 0 P10 R/W 0 Bit 0 P20 R/W 0 Bit 0 P50 R/W 0
Note: The P02 keeps "1" when external reset enable by code option.
Example: Read data from input port. B0MOV A, P0 B0MOV A, P1 B0MOV A, P5 Example: Write data to output port. MOV A, #0FFH B0MOV P0, A B0MOV P1, A B0MOV P5, A Example: Write one bit data to output port. B0BSET P1.3 B0BSET P5.5 B0BCLR B0BCLR P1.3 P5.5
; Read data from Port 0 ; Read data from Port 1 ; Read data from Port 5 ; Write data FFH to all Port.
; Set P1.3 and P5.5 to be "1". ; Set P1.3 and P5.5 to be "0".
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7.5 PORT1, PORT2 APPLICATION CIRCUIT
SN8P2614 provides Port 1 and Port 2 for LED panel driving. P1 drain current is 15mA like normal GPIO, and control each dot of one 7-segment as SEG type. P2 has 200mA sink current to control each 7-segment's power of LED panel as COM type. The application is as following.
POWER
VCC C1 47uF C2 0.1uF VSS VDD
Ext. RESET
VDD R9 47K RST C5 0.1uF VSS
Ext. OSC
XIN C4 20pF ?MHz VSS Y1 XOUT C3 20pF
R1 R2 R3 R4 R5 R6 R7 R8
P5.0 P5.1 P5.2 P5.3 P5.4 VDD 330 330 330 330 330 330 330 330
1 2 3 4 5 6 7 8 9 10 11 12 13 14
U1 P0.1/INT1 P5.0 P0.0/INT0 P5.1 P0.2/RST/VPP P5.2 XIN/P0.3 P5.3/BZ1/PWM1 XOUT/P0.4 P5.4 VSS VDD P2.7 P1.0 P2.6 P1.1 P1.2 P2.5 P1.3 P2.4 P1.4 P2.3 P1.5 P2.2 P1.6 P2.1 P1.7 P2.0 SN8P2614
U
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P0.1 P0.0 RST XIN XOUT VSS
LED SEG
LED COM
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8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V). Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec). VDD 3V 5V Internal Low RC Freq. 16KHz 32KHz Watchdog Overflow Time 512ms 256ms
Note: If watchdog is "Always_On" mode, it keeps running event under power down mode or green mode.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer. 0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR Read/Write W W W W W W W After reset 0 0 0 0 0 0 0
Bit 0 WDTR0 W 0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: MOV B0MOV ... CALL CALL ... ... ... JMP A,#5AH WDTR,A SUB1 SUB2 ; Clear the watchdog timer.
MAIN
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Watchdog timer application note is as following. Before clearing watchdog timer, check I/O status and check RAM contents can improve system error. Don't clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail. Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: Err: Correct: B0BSET ... CALL CALL ... ... ... JMP FWDRST SUB1 SUB2 ... ... JMP $ ; Check I/O. ; Check RAM ; I/O or RAM error. Program jump here and don't ; clear watchdog. Wait watchdog timer overflow to reset IC. ; I/O and RAM are correct. Clear watchdog timer and ; execute program. ; Only one clearing watchdog timer of whole program.
MAIN
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8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger T0 interrupt to request interrupt service. The main purposes of the T0 timer is as following. 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected clock frequency. RTC timer: Generates interrupts at real time intervals based on the selected clock source. RTC function is only available in High_Clk code option = "IHRC_RTC". Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by T0 time out.
T0 Rate (Fcpu/2~Fcpu/256)
T0ENB
Internal Data Bus Load T0TB
Fcpu
T0C 8-Bit Binary Up Counting Counter
CPUM0,1
T0 Time Out
RTC
T0ENB
Note:1. In RTC mode, clear T0IRQ must be after 1/2 RTC clock source (32768Hz), or the RTC interval time is error. The delay is about 16us and use T0 interrupt service routine executing time to be the 16us delay time. 2. In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts.
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8.2.2 T0M MODE REGISTER
0D8H T0M Read/Write After reset Bit 0 Bit 7 T0ENB R/W 0 Bit 6 T0rate2 R/W 0 Bit 5 T0rate1 R/W 0 Bit 4 T0rate0 R/W 0 Bit 3 Bit 2 Bit 1 Bit 0 T0TB R/W 0
T0TB: RTC clock source control bit. 0 = Disable RTC (T0 clock source from Fcpu). 1 = Enable RTC. T0RATE[2:0]: T0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ... 110 = fcpu/4. 111 = fcpu/2. T0ENB: T0 counter control bit. 0 = Disable T0 timer. 1 = Enable T0 timer. Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
Bit [6:4]
Bit 7
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8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control. 0D9H Bit 7 Bit 6 Bit 5 Bit 4 T0C7 T0C6 T0C5 T0C4 T0C Read/Write R/W R/W R/W R/W After reset 0 0 0 0 The equation of T0C initial value is as following. T0C initial value = 256 - (T0 interrupt interval time * input clock) Bit 3 T0C3 R/W 0 Bit 2 T0C2 R/W 0 Bit 1 T0C1 R/W 0 Bit 0 T0C0 R/W 0
Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select T0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10-2 * 4 * 106 / 4 / 64) = 100 = 64H
The basic timer table interval time of T0. High speed mode (Fcpu = 4MHz / 4) T0RATE T0CLOCK Max overflow interval One step = max/256 000 Fcpu/256 65.536 ms 256 us 001 Fcpu/128 32.768 ms 128 us 010 Fcpu/64 16.384 ms 64 us 011 Fcpu/32 8.192 ms 32 us 100 Fcpu/16 4.096 ms 16 us 101 Fcpu/8 2.048 ms 8 us 110 Fcpu/4 1.024 ms 4 us 111 Fcpu/2 0.512 ms 2 us
Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31250 us 4000 ms 15625 us 2000 ms 7812.5 us 1000 ms 3906.25 us 500 ms 1953.125 us 250 ms 976.563 us 125 ms 488.281 us 62.5 ms 244.141 us
Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don't change T0C value in RTC mode.
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8.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following. Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag. B0BCLR B0BCLR B0BCLR Set T0 timer rate. MOV B0MOV A, #0xxx0000b T0M,A ;The T0 rate control bits exist in bit4~bit6 of T0M. The ; value is from x000xxxxb~x111xxxxb. ; T0 timer is disabled. FT0ENB FT0IEN FT0IRQ ; T0 timer. ; T0 interrupt function is disabled. ; T0 interrupt request flag is cleared.
Set T0 clock source from Fcpu or RTC. B0BCLR or B0BSET FT0TB ; Select T0 RTC clock source. FT0TB ; Select T0 Fcpu clock source.
Set T0 interrupt interval time. MOV B0MOV Set T0 timer function mode. B0BSET Enable T0 timer. B0BSET FT0ENB ; Enable T0 timer. FT0IEN ; Enable T0 interrupt function. A,#7FH T0C,A ; Set T0C value.
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8.3 TIMER/COUNTER 0 (TC1)
8.3.1 OVERVIEW
The TC1 is an 8-bit binary up counting timer with double buffers. TC1 has two clock sources including internal clock and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT1 from P0.1 pin (Falling edge trigger). Using TC1M register selects TC1C's clock source from internal or external. If TC1 timer occurs an overflow, it will continue counting and issue a time-out signal to trigger TC1 interrupt to request interrupt service. TC1 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits. The main purposes of the TC1 timer is as following. 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected clock frequency. External event counter: Counts system "events" based on falling edge detection of external clock signals at the INT1 input pin. Buzzer output PWM output
TC1OUT Internal P5.3 I/O Circuit Up Counting Reload Value ALOAD1 Buzzer TC1 Time Out Auto. Reload TC1 / 2 P5.3
TC1R Reload Data Buffer TC1 Rate (Fcpu/2~Fcpu/256) TC1CKS Fcpu TC1ENB Load TC1C 8-Bit Binary Up Counting Counter INT1 (Schmitter Trigger) CPUM0,1 Compare S R
ALOAD1, TC1OUT PWM1OUT PWM
TC1 Time Out
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8.3.2 TC1M MODE REGISTER
0DCH TC1M Read/Write After reset Bit 0 Bit 7 TC1ENB R/W 0 Bit 6 TC1rate2 R/W 0 Bit 5 TC1rate1 R/W 0 Bit 4 TC1rate0 R/W 0 Bit 3 TC1CKS R/W 0 Bit 2 ALOAD1 R/W 0 Bit 1 TC1OUT R/W 0 Bit 0 PWM1OUT R/W 0
PWM1OUT: PWM output control bit. 0 = Disable PWM output. 1 = Enable PWM output. PWM duty controlled by TC1OUT, ALOAD1 bits. TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM1OUT = 0. 0 = Disable, P5.3 is I/O function. 1 = Enable, P5.3 is output TC1OUT signal. ALOAD1: Auto-reload control bit. Only valid when PWM1OUT = 0. 0 = Disable TC1 auto-reload function. 1 = Enable TC1 auto-reload function. TC1CKS: TC1 clock source select bit. 0 = Internal clock (Fcpu or Fosc). 1 = External clock from P0.1/INT1 pin. TC1RATE[2:0]: TC1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ... 110 = fcpu/4. 111 = fcpu/2. TC1ENB: TC1 counter control bit. 0 = Disable TC1 timer. 1 = Enable TC1 timer. Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0).
Bit 1
Bit 2
Bit 3
Bit [6:4]
Bit 7
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8.3.3 TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for TC1 interval time control. 0DDH TC1C Read/Write After reset Bit 7 TC1C7 R/W 0 Bit 6 TC1C6 R/W 0 Bit 5 TC1C5 R/W 0 Bit 4 TC1C4 R/W 0 Bit 3 TC1C3 R/W 0 Bit 2 TC1C2 R/W 0 Bit 1 TC1C1 R/W 0 Bit 0 TC1C0 R/W 0
The equation of TC1C initial value is as following. TC1C initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow table.
TC1CKS PWM1 ALOAD1 TC1OUT 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 -
N
256 256 64 32 16 256
0
1
TC1C valid value 0x00~0xFF 0x00~0xFF 0x00~0x3F 0x00~0x1F 0x00~0x0F 0x00~0xFF
TC1C value binary type 00000000b~11111111b 00000000b~11111111b xx000000b~xx111111b xxx00000b~xxx11111b xxxx0000b~xxxx1111b 00000000b~11111111b
Remark Overflow per 256 count Overflow per 256 count Overflow per 64 count Overflow per 32 count Overflow per 16 count Overflow per 256 count
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
TC1C initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10-2 * 4 * 106 / 4 / 64) = 100 = 64H
The basic timer table interval time of TC1. High speed mode (Fcpu = 4MHz / 4) TC1RATE TC1CLOCK Max overflow interval One step = max/256 000 Fcpu/256 65.536 ms 256 us 001 Fcpu/128 32.768 ms 128 us 010 Fcpu/64 16.384 ms 64 us 011 Fcpu/32 8.192 ms 32 us 100 Fcpu/16 4.096 ms 16 us 101 Fcpu/8 2.048 ms 8 us 110 Fcpu/4 1.024 ms 4 us 111 Fcpu/2 0.512 ms 2 us
Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31250 us 4000 ms 15625 us 2000 ms 7812.5 us 1000 ms 3906.25 us 500 ms 1953.125 us 250 ms 976.563 us 125 ms 488.281 us 62.5 ms 244.141 us
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8.3.4 TC1R AUTO-LOAD REGISTER
TC1 timer is with auto-load function controlled by ALOAD1 bit of TC1M. When TC1C overflow occurring, TC1R value will load to TC1C by system. It is easy to generate an accurate time, and users don't reset TC1C during interrupt service routine. TC1 is double buffer design. If new TC1R value is set by program, the new value is stored in 1st buffer. Until TC1 overflow occurs, the new value moves to real TC1R buffer. This way can avoid TC1 interval time error and glitch in PWM and Buzzer output. Note: Under PWM mode, auto-load is enabled automatically. The ALOAD1 bit is selecting overflow boundary.
0DEH TC1R Read/Write After reset
Bit 7 TC1R7 W 0
Bit 6 TC1R6 W 0
Bit 5 TC1R5 W 0
Bit 4 TC1R4 W 0
Bit 3 TC1R3 W 0
Bit 2 TC1R2 W 0
Bit 1 TC1R1 W 0
Bit 0 TC1R0 W 0
The equation of TC1R initial value is as following. TC1R initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow table.
TC1CKS PWM1 ALOAD1 TC1OUT 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 -
N
256 256 64 32 16 256
0
1
TC1R valid value 0x00~0xFF 0x00~0xFF 0x00~0x3F 0x00~0x1F 0x00~0x0F 0x00~0xFF
TC1R value binary type 00000000b~11111111b 00000000b~11111111b xx000000b~xx111111b xxx00000b~xxx11111b xxxx0000b~xxxx1111b 00000000b~11111111b
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10-2 * 4 * 106 / 4 / 64) = 100 = 64H
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8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC1OUT) is from TC1 timer/counter frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1OUT frequency is divided by 2 from TC1 interval time. TC1OUT frequency is 1/2 TC1 frequency. The TC1 clock has many combinations and easily to make difference frequency. The TC1OUT frequency waveform is as following.
1
2
3
4
TC0 Overflow Clock
1
2
3
4
TC0OUT (Buzzer) Output Clock
Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The TC1OUT frequency is 0.5KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 1KHz. The TC1 clock source is from external oscillator clock. T0C rate is Fcpu/8. The TC1RATE2~TC1RATE1 = 101. TC1C = TC1R = 131. MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET A,#01010000B TC1M,A A,#131 TC1C,A TC1R,A FTC1OUT FALOAD1 FTC1ENB ; Set the TC1 rate to Fcpu/4 ; Set the auto-reload reference value
; Enable TC1 output to P5.3 and disable P5.3 I/O function ; Enable TC1 auto-reload function ; Enable TC1 timer
Note: Buzzer output is enable, and "PWM1OUT" must be "0".
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8.3.6 TC1 TIMER OPERATION SEQUENCE
TC1 timer operation includes timer interrupt, event counter, TC1OUT and PWM. The sequence of setup TC1 timer is as following. Stop TC1 timer counting, disable TC1 interrupt function and clear TC1 interrupt request flag. B0BCLR B0BCLR B0BCLR FTC1ENB FTC1IEN FTC1IRQ ; TC1 timer, TC1OUT and PWM stop. ; TC1 interrupt function is disabled. ; TC1 interrupt request flag is cleared.
Set TC1 timer rate. (Besides event counter mode.) MOV B0MOV Set TC1 timer clock source. ; Select TC1 internal / external clock source. B0BCLR FTC1CKS or B0BSET FTC1CKS ; Select TC1 internal clock source. ; Select TC1 external clock source. A, #0xxx0000b TC1M,A ;The TC1 rate control bits exist in bit4~bit6 of TC1M. The ; value is from x000xxxxb~x111xxxxb. ; TC1 interrupt function is disabled.
Set TC1 timer auto-load mode. B0BCLR or B0BSET FALOAD1 ; Disable TC1 auto reload function. FALOAD1 ; Enable TC1 auto reload function.
Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty cycle. ; Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty. MOV A,#7FH ; TC1C and TC1R value is decided by TC1 mode. B0MOV TC1C,A ; Set TC1C value. B0MOV TC1R,A ; Set TC1R value under auto reload mode or PWM mode. ; In PWM mode, set PWM cycle. B0BCLR B0BCLR or B0BCLR B0BSET or B0BSET B0BCLR or B0BSET B0BSET FALOAD1 FTC1OUT FALOAD1 FTC1OUT FALOAD1 FTC1OUT FALOAD1 FTC1OUT ; ALOAD1, TC1OUT = 00, PWM cycle boundary is ; 0~255. ; ALOAD1, TC1OUT = 01, PWM cycle boundary is ; 0~63. ; ALOAD1, TC1OUT = 10, PWM cycle boundary is ; 0~31. ; ALOAD1, TC1OUT = 11, PWM cycle boundary is ; 0~15.
Set TC1 timer function mode. B0BSET or B0BSET or B0BSET Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. FPWM1OUT ; Enable PWM function. FTC1OUT ; Enable TC1OUT (Buzzer) function. FTC1IEN ; Enable TC1 interrupt function.
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8.4 PWM1 MODE
8.4.1 OVERVIEW
PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit counter counts modulus 256, 64, 32, 16 controlled by ALOAD1, TC1OUT bits. The value of the 8-bit counter (TC1C) is compared to the contents of the reference register (TC1R). When the reference register value (TC1R) is equal to the counter value (TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the PWM1 output is TC1R/256, 64, 32, 16. PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM's duty cycle is to modify the TC1R. Note: TC1 is double buffer design. Modifying TC1R to change PWM duty by program, there is no glitch and error duty signal in PWM output waveform. Users can change TC1R any time, and the new reload value is loaded to TC1R buffer at TC1 overflow.
ALOAD1 TC1OUT PWM duty range 0 0 1 1 0 1 0 1 0/256~255/256 0/64~63/64 0/32~31/32 0/16~15/16
TC1C valid value TC1R valid bits value 0x00~0xFF 0x00~0x3F 0x00~0x1F 0x00~0x0F 0x00~0xFF 0x00~0x3F 0x00~0x1F 0x00~0x0F
MAX. PWM Frequency (Fcpu = 4MHz) 7.8125K 31.25K 62.5K 125K
Remark Overflow per 256 count Overflow per 64 count Overflow per 32 count Overflow per 16 count
The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256.
0 1 ...... 128 ...... 254 255 0 1 ...... 128 ...... 254 255
TC1 Clock
TC1R=00H
Low High Low High Low High Low
TC1R=01H
TC1R=80H
TC1R=FFH
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8.4.2 TCxIRQ and PWM Duty
In PWM mode, the frequency of TC1IRQ is depended on PWM duty range. From following diagram, the TC1IRQ frequency is related with PWM duty.
TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~255)
TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~63)
TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~31)
TC1 Overflow, TC1IRQ = 1 0xFF TC1C Value 0x00 PWM1 Output (Duty Range 0~15)
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8.4.3 PWM Duty with TCxR Changing
In PWM mode, the system will compare TC1C and TC1R all the time. When TC1CTC1C = TC1R
TC1C overflow and TC1IRQ set
0xFF TC1C Value 0x00
PWM1 Output
Period
1
2
3
4
5
6
7
Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output "High, when TC1C TC1R PWM output "Low". If TC1R is changing in the program processing, the PWM waveform will became as following diagram.
TC1C < TC1R PWM Low > High TC1C > = TC1R PWM High > Low TC1C overflow and TC1IRQ set
Update New TC1R! Old TC1R < TC1C < New TC1R Update New TC1R! New TC1R < TC1C < Old TC1R New TC1R Old TC1R
0xFF TC1C Value 0x00
Old TC1R
New TC1R
PWM1 Output
Period
1 1st PWM
2 Update PWM Duty
3 2nd PWM
4 Update PWM Duty
5 3th PWM
In period 2 and period 4, new Duty (TC1R) is set. TC1 is double buffer design. The PWM still keeps the same duty in period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.
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8.4.4 PWM PROGRAM EXAMPLE
Example: Setup PWM1 output from TC1 to PWM1OUT (P5.3). The external high-speed oscillator clock is 4MHz. Fcpu = Fosc/4. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 30. MOV B0MOV MOV B0MOV B0MOV B0BCLR B0BCLR B0BSET B0BSET A,#01100000B TC1M,A A,#30 TC1C,A TC1R,A FTC1OUT FALOAD1 FPWM1OUT FTC1ENB ; Set the TC1 rate to Fcpu/4 ; Set the PWM duty to 30/256
; Set duty range as 0/256~255/256. ; Enable PWM1 output to P5.3 and disable P5.3 I/O function ; Enable TC1 timer
Note: The TC1R is write-only register. Don't process them using INCMS, DECMS instructions.
Example: Modify TC1R registers' value. MOV B0MOV INCMS NOP B0MOV B0MOV A, #30H TC1R, A BUF0 A, BUF0 TC1R, A ; Input a number using B0MOV instruction. ; Get the new TC1R value from the BUF0 buffer defined by ; programming.
Note: The PWM can work with interrupt request.
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9
Field M O V E A R I T H M E T I C L O G I C
INSTRUCTION TABLE
Mnemonic MOV A,M MOV M,A B0MOV A,M B0MOV M,A MOV A,I B0MOV M,I XCH A,M B0XCH A,M MOVC ADC ADC ADD ADD B0ADD ADD SBC SBC SUB SUB SUB AND AND AND OR OR OR XOR XOR XOR SWAP SWAPM RRC RRCM RLC RLCM CLR BCLR BSET B0BCLR B0BSET CMPRS CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 JMP CALL A,M M,A A,M M,A M,A A,I A,M M,A A,M M,A A,I A,M M,A A,I A,M M,A A,I A,M M,A A,I M M M M M M M M.b M.b M.b M.b A,I A,M M M M M M.b M.b M.b M.b d d Description AM MA A M (bank 0) M (bank 0) A AI M I, "M" only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z...) A M A M (bank 0) R, A ROM [Y,Z] A A + M + C, if occur carry, then C=1, else C=0 M A + M + C, if occur carry, then C=1, else C=0 A A + M, if occur carry, then C=1, else C=0 M A + M, if occur carry, then C=1, else C=0 M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0 A A + I, if occur carry, then C=1, else C=0 A A - M - /C, if occur borrow, then C=0, else C=1 M A - M - /C, if occur borrow, then C=0, else C=1 A A - M, if occur borrow, then C=0, else C=1 M A - M, if occur borrow, then C=0, else C=1 A A - I, if occur borrow, then C=0, else C=1 A A and M M A and M A A and I A A or M M A or M A A or I A A xor M M A xor M A A xor I A (b3~b0, b7~b4) M(b7~b4, b3~b0) M(b3~b0, b7~b4) M(b7~b4, b3~b0) A RRC M M RRC M A RLC M M RLC M M0 M.b 0 M.b 1 M(bank 0).b 0 M(bank 0).b 1 ZF,C A - I, If A = I, then skip next instruction ZF,C A - M, If A = M, then skip next instruction A M + 1, If A = 0, then skip next instruction M M + 1, If M = 0, then skip next instruction A M - 1, If A = 0, then skip next instruction M M - 1, If M = 0, then skip next instruction If M.b = 0, then skip next instruction If M.b = 1, then skip next instruction If M(bank 0).b = 0, then skip next instruction If M(bank 0).b = 1, then skip next instruction PC15/14 RomPages1/0, PC13~PC0 d Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d C DC Z Cycle 1 1 1 1 1 1 1+N 1+N 2 1 1+N 1 1+N 1+N 1 1 1+N 1 1+N 1 1 1+N 1 1 1+N 1 1 1+N 1 1 1+N 1 1+N 1 1+N 1 1+N 1+N 1+N 1+N 1+S 1+S 1+ S 1+N+S 1+ S 1+N+S 1+S 1+S 1+S 1+S 2 2 2 2 1 1 1
P R O C E S S
B R A N C H
RET PC Stack RETI PC Stack, and to enable global interrupt PUSH To push ACC and PFLAG (except NT0, NPD bit) into buffers. POP To pop ACC and PFLAG (except NT0, NPD bit) from buffers. NOP No operation Note: 1. "M" is system register or RAM. If "M" is system registers then "N" = 0, otherwise "N" = 1. 2. If branch condition is true then "S = 1", otherwise "S = 0". M I S C
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10 ELECTRICAL CHARACTERISTIC
10.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd)....................................................................................................................................................... - 0.3V ~ 6.0V Input in voltage (Vin)........................................................................................................................................ Vss - 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr) SN8P2614P, SN8P2614S, SN8P2614X .................................................................................................................... 0C ~ + 70C SN8P2614PD, SN8P2614SD, SN8P2614XD ..............................................................................................................-40C ~ + 85C Storage ambient temperature (Tstor) ............................................................................................................................ -40C ~ + 125C
10.2 ELECTRICAL CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, fosc = 4MHz,Fcpu=1MHZ, ambient temperature is 25C unless otherwise note.) PARAMETER SYM. DESCRIPTION MIN. TYP. MAX. Operating voltage RAM Data Retention voltage Vdd rise rate Input Low Voltage Input High Voltage Reset pin leakage current I/O port pull-up resistor I/O port input leakage current I/O output source current sink current INTn trigger pulse width Vdd Vdr Vpor ViL1 ViL2 ViH1 ViH2 Ilekg Rup Ilekg IoH IoL1 IoL2 Tint0 Idd1 Idd2 Supply Current Idd3 Sleep Mode Normal mode, Vpp = Vdd Vdd rise rate to ensure internal power-on reset All input ports Reset pin All input ports Reset pin Vin = Vdd Vin = Vss , Vdd = 3V Vin = Vss , Vdd = 5V Pull-up resistor disable, Vin = Vdd Vop = Vdd - 0.5V Vop = Vss + 0.5V Vop = Vss + 1.5V, Port 2 only. INT0 interrupt request pulse width normal Mode (No loading, Fcpu = Fosc/4) Slow Mode (Internal low RC) Vdd= 5V, 4Mhz Vdd= 3V, 4Mhz Vdd= 5V, 32Khz Vdd= 3V, 16Khz Vdd= 5V, 25C Vdd= 3V , 25C Vdd= 5V, -40~85C Vdd= 3V , -40~85C Vdd= 5V, 4Mhz Vdd= 3V, 4Mhz LVD 1.5 0.05 Vss Vss 0.7Vdd 0.8Vdd 100 50 2/fcpu 15.68 5.0 200 100 15* 15* 200* 2.5 1 20 5 0.8 0.7 10 10 0.6 0.25 15 3 16 5.5 0.3Vdd 0.2Vdd Vdd Vdd 2 300 150 2 5 2 40 10 1.6 1.4 21 21 1.2 0.5 30 6 16.32 UNIT V V V/ms V V V V uA K uA mA cycle mA mA uA uA uA uA uA uA mA mA uA uA Mhz
Idd4
Internal High Oscillator Freq.
Fihrc
Vdet0 LVD Voltage Vdet1 Vdet2
Vdd=5V, ILRC 32Khz Vdd=3V, ILRC 16Khz 25C, Vdd= 5V, Fcpu = 1MHz Internal Hihg RC (IHRC) -40C~85C, Vdd= 2.4V~5.5V, Fcpu = 1MHz~16 MHz Low voltage reset level. Low voltage reset level. Fcpu = 1 MHz. Low voltage indicator level. Fcpu = 1 MHz. Low voltage indicator level. Fcpu = 1 MHz
Green Mode (No loading, Fcpu = Fosc/4 Watchdog Disable)
13 1.6 2.0 2.7
16 2.0 2.3 3.3
19 2.3 3 4.5
Mhz V V V
*These parameters are design guarantee and characterized but not tested.
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11 OTP PROGRAMMING PIN
11.1 The pin assignment of Easy Writer transition board socket:
Easy Writer JP1/JP2 VSS 2 CE 4 OE/ShiftDat 6 D0 8 D2 10 D4 12 D6 14 VPP 16 RST 18 ALSB/PDB 20 1 VDD 3 CLK/PGCLK 5 PGM/OTPCLK 7 D1 9 D3 11 D5 13 D7 15 VDD 17 HLS 19 Easy Writer JP3 (Mapping to 48-pin text tool) DIP1 1 48 DIP48 DIP2 2 47 DIP47 DIP3 3 46 DIP46 DIP4 4 45 DIP45 DIP5 5 44 DIP44 DIP6 6 43 DIP43 DIP7 7 42 DIP42 DIP8 8 41 DIP41 DIP9 9 40 DIP40 DIP10 10 39 DIP39 DIP11 11 38 DIP38 DIP12 12 37 DIP38 DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP28 DIP22 22 27 DIP27 DIP23 23 26 DIP26 DIP24 24 25 DIP25 JP3 for MP transition board
JP1 for MP transition board JP2 for Writer V3.0 transition board
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11.2 Programming Pin Mapping:
Programming Information of SN8P2614 Series Chip Name SN8P2614P/S/X EZ Writer / Writer Writer V2.5 OTP IC / JP3 Pin Assigment V3.0 Connector Connector Number Name Number Name Number Pin Number Pin Number Pin 2 VDD 1 VDD 6 VDD 1 GND 2 GND 23 VSS 4 CLK 3 CLK 1 P5.0 3 CE 4 CE 6 PGM 5 PGM 7 P1.0 5 OE 6 OE 2 P5.1 8 D1 7 D1 7 D0 8 D0 10 D3 9 D3 9 D2 10 D2 12 D5 11 D5 11 D4 12 D4 14 D7 13 D7 13 D6 14 D6 16 VDD 15 VDD 15 VPP 16 VPP 26 RST 18 HLS 17 HLS 17 RST 18 RST 19 20 ALSB/PDB 8 P1.1
Number
Pin
Note:Use M2IDE V1.11 (or after version) to simulation. Note: Use 16M Hz Crystal to simulation internal 16M RC. Note: Use 16M Hz Crystal to programming with EZWriter.
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8-Bit Micro-Controller
12 PACKAGE INFORMATION
12.1 SK-DIP 28 PIN
SYMBOLS A A1 A2 D E E1 L
MIN 0.015 0.114 1.390 0.283 0.115 0.330 0
NOR (inch) 0.130 1.390 0.310 0.288 0.130 0.350 7
MAX 0.210 0.135 1.400 0.293 0.150 0.370 15
MIN 0.381 2.896 35.306 7.188 2.921 8.382 0
NOR (mm) 3.302 35.306 7.874 7.315 3.302 8.890 7
MAX 5.334 3.429 35.560 7.442 3.810 9.398 15
B
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12.2 SOP 28 PIN
SYMBOLS A A1 D E H L
MIN 0.093 0.004 0.697 0.291 0.394 0.016 0
NOR (inch) 0.099 0.008 0.705 0.295 0.407 0.033 4
MAX 0.104 0.012 0.713 0.299 0.419 0.050 8
MIN 2.362 0.102 17.704 7.391 10.008 0.406 0
NOR (mm) 2.502 0.203 17.907 7.493 10.325 0.838 4
MAX 2.642 0.305 18.110 7.595 10.643 1.270 8
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12.3 SSOP 28 PIN
SYMBOLS A A1 A2 b C D E E1 [e] L R
MIN 0.00 0.06 0.01 0.00 0.39 0.29 0.20 0.02 0.00 0
NOR (inch) 0.07 0.40 0.31 0.21 0.0259BSC 0.04 4
MAX 0.08 0.01 0.07 0.01 0.01 0.41 0.32 0.22 0.04 8
MIN 0.05 1.63 0.22 0.09 9.90 7.40 5.00 0.63 0.09 0
NOR (mm) 1.75 10.20 7.80 5.30 0.65BSC 0.90 4
MAX 2.13 0.25 1.88 0.38 0.20 10.50 8.20 5.60 1.03 8
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13 Marking Definition
13.1 INTRODUCTION
There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU.
13.2
MARKING INDETIFICATION SYSTEM
SN8 X PART No. X X X
Material Temperature Range Shipping Package
B = PB-Free Package G = Green Package - = 0 ~ 70 D = -40 ~ 85 W = Wafer H = Dice K = SK-DIP S = SOP X = SSOP
Device
2614
ROM Type Title
P=OTP
SONiX 8-bit MCU Production
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8-Bit Micro-Controller
13.3
MARKING EXAMPLE
ROM Type OTP OTP Device 2614 2614 Package SK-DIP SOP Temperature 0~70 0~70 Material PB-Free Package PB-Free Package
Name SN8P2614KB SN8P2614SB
13.4 DATECODE SYSTEM
X X X X XXXXX
SONiX Internal Use Day
1=01 2=02 .... 9=09 A=10 B=11 .... 1=January 2=February .... 9=September A=October B=November C=December 03= 2003 04= 2004 05= 2005 06= 2006 ....
Month
Year
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8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180
Hong Kong Office:
AUnit No.705,Level 7 Tower 1,Grand Central Plaza 138 Shatin Rural Committee Road,Shatin,New Territories,Hong Kong. Tel:(852)2723-8086 Fax:(852)2723-9179
Technical Support by Email:
Sn8fae@sonix.com.tw
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